loberman

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loberman last won the day on January 14 2018

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  1. Been meaning to document the manual Linux on Arty without petalinux fully so finally here it is. I attached a PDF file as its easier to do it that way. Any questions ask away. Firstly thanks to Jeff of http://www.fpgadeveloper.com as I used his base design as the start, see above. Ping me oberman.l@gmail.com for files, too large to attach here Linux_on_artA7_manual_build.pdf
  2. loberman

    Arty-S7?

    Now that the arty-S7 is out, yep no Ethernet I have Linux running on it manual build, not using Petalinux Steps -------- Use the base design from the Digilent github Create and build the fsbl project (tar file attached) Ensure bitstream has the elf file associated Use the SDK to also create the DTS files and merge them copy the final to kernel_src_dir/arch/microblaze/boot/dts/artylinux.dts Build the kernel #cat build_it.sh export CROSS_COMPILE=microblazeel-xilinx-linux-gnu- make ARCH=microblaze clean make ARCH=microblaze simpleImage.artylinux -j8 cp arch/microblaze/boot/simpleImage.artylinux . cp simpleImage.artylinux .. cd .. #(root of project) mb-objcopy -O binary simpleImage.artylinux artylinux.bin Use this example tcl to create the mcs file set_property BITSTREAM.Config.SPI_BUSWIDTH 4 [current_design] write_bitstream /data/Xilinx/Arty-S7-50-base/download.bit -force write_cfgmem -format mcs -size 16 -interface SPIx4 -loadbit {up 0x00000000 "/data/Xilinx/Arty-S7-50-base/download.bit" } -loaddata {up 0x00500000 "/data/Xilinx/Arty-S7-50-base/artylinux.bin" } -force -file "/data/Xilinx/Arty-S7-50-base/lemicro.mcs" Reset and Linux will boot fsbl.tar.xz
  3. loberman

    Zybo Ethernet example

    If you build a Zybo design from scratch you have to change the emio to mio for the Ethernet or wilt will not work. It defaults to emio See http://igorfreire.com.br/zynq-ethernet-interface-zybo-board/#Media_IndependentInterface_between_the_MAC_and_the_PHY
  4. Finally got a website where I can put this all. Have to document and then will add the link.
  5. The original credit for the Zybo goes the Eli. He has excelelnt information on his site. http://billauer.co.il/blog/2014/07/bash-gpio-xillinux/
  6. Hello Thanks yep for ZYBO its a lot easier, I have done that already. The access is made easier with the built in ARM processor on the ZYBO. The challenge is the microblaze and AXI. I am working on it now, I hacked the pmodSD stuff and will and whatever I figure out to this post
  7. Hello Gau_Veldt You bring up an interesting point here for the Embedded Linux kernel interfacing to the PMOD Right now I have access to all switches, LED and all the shield pins via the gpio interfaces on Linux that use AXI. When one uses the Digilent IP to expose a PMOD jA to jd for example, you have to choose a pmod module however. I want the same IP connected to the AXI bus but direct to the pmod so I can use the Linux GPIO driver to get the the native pins of a pmod interface. From your post you seem to know how to do that. I was thinking of taking the most simple pmod connection and modifying the HDL. If not I will have to write my one driver, but figured I would ask first. Regards Laurence
  8. I am working on a blog with all I have done to get Linux working with manual kernel builds etc.on Arty. Once I have a home for the blog will include the link. It took a long time and got a lot of help from this forum so happy to share
  9. Within Vivado you would go to the board tab and click on the particular pmod for the nexys4. Then choose what type of pmod ypu will plug into that pmod port. Digilent has pro-actively supplied the IP in the Vivado library so when you choose a pmod the IP will get included and Vivado will offer to auto configure it. Let it do that and you will be all set. I am using Linux to drive the pins via gpio and the 10Mhz was a separate clock I needed for my project. Thanks Laurence
  10. I confirmed all is well on the scope and the 10Mhz is on the output pin. Scope frequency slightly varies as expected between 9.9 and 10.1 Mhz but its clearly working as it should. If you just want to interface from the fabric of the FPGA to the PMOD pin its easier as Jon has shown to just use a constraint base don the Pin# Use the Digilent provided xdc file for the Nexys4 to get your pin numbers.
  11. Hi Well. its not much code, its exactly what Jon suggested I do. I added another output clock of 10Mhz to the clock wizard I then created a port as a clock output and connected the clk to the port The JA Header notes say G13 is ja[0] so I constrained that below ##Pmod Header JA #set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0_15 Sch=ja[1] set_property IOSTANDARD LVCMOS33 [get_ports pmod_ja_clk] set_property PACKAGE_PIN G13 [get_ports pmod_ja_clk] I am about to connect an Oscilloscope to the ja[0] pin to check the output. Everything synthesized and worked to create the bitstream. I did not use any of the board JA IP, for this but I am using the IP for JC for the pmodOled. This is somewhat of complex of a design because its running Linux as well.
  12. OK Thanks I am using your method and its working. Thanks
  13. Hello Jon Yep I can do it this way. However what is the pmod bridge used for. It was in the drop-down when I added JA. Wondering because I see both I and o pins on that IP so was wondering. Thanks Laurence
  14. Hello I only now got time to start trying these suggestions , but I then came across the pmod BRIDGE IP. Is that documented somewhere ?. Seems that may be one way to add the clock to a pmod pin ? Thanks Laurence
  15. Hello thanks all for these valuable inputs. Is your IP publicly available. The one you mentioned above. Many thanks Laurence