Azurath

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Everything posted by Azurath

  1. Hello! I have an example design where I am writing values into a BRAM. I have confirmed through simulation that the values are stored correctly. However, what I want to do is to confirm that the values are saved running on hardware as well? I have been trying to debug using the TCF debugger and trying to check the Memory window on the uB but I am not getting anything sufficient or understandable. What should I do if I want to, for example, test my memory through the MicroBlaze, shall the D-cache and I-cache be enabled? Could you giv
  2. Ok, found the example design concerning simulating the VDMA. If you place the VDMA block inside your block design, right click and press "open IP example" and dadam you will get the example design that contains the testbench for simulating the VDMA ( example design from the datasheet). I guess I can move further from there. Thx for the extra material though.
  3. Hello, dear FPGA enthusiasts! Currently, I have been working with my OV7670 camera and can present it on an HDMI screen. However, this was done without a simulation. What I want to do right now is to use a TPG provided from Xlinix in my design and remove the OV7670 fully. However, the problem is that I really don't know how to go next since I am using uB together with a VDMA and TPG. I know that you can include the ELF file from the uB in order to simulate your design together with uB. My question to you is where I can find C code for the TPG used in the ne
  4. Yes I was actually struggling alot but I am not afraid of something just because it is complicated. Life is complicated itself, further we have Girls that are more complicated than the DDR3 algorithm itself :). Anyhow I want to see whether the picture I stored is saved in the SDRAM DDR3 and want to debug it somehow. My second thought is to use the UART and the processing IDE to print the picture but I don’t know any other way to confirm that the DDR3 has stored all the pixel values correctly. Is there professional ways to debug a DDR3? Regards, John
  5. Hello! I cannot debug the DDR3 outputs/inputs. I get the following error message. Bus interface connection '/mig_7series_0_DDR3' is connected to interface '/mig_7series_0/DDR3' with VLNV xilinx.com:interface:ddrx:1.0, which is not debug-able by System ILA IP. HDL attribute 'DEBUG' will not be set to this bus interface connection. Could anybody help me with this? I am going to check if my 640x480 picture is saved in the ddr3 but I have to use the ILA which does not work atm. regards, John
  6. Nope , I also had to upgrade the IPs so the block generation works now thx.
  7. Hello! I get the following error when I am going to run the createproject.tcl. Do I have to download an earlier version than 2017.3, if so is there a way to not do it since it takes me a lot of time to (uninstall and install) different versions. The error is: [Board 49-71] The board_part definition was not found for digilentinc.com:nexys_video:part0:1.1. The project's board_part property was not set, but the project's part property was set to xc7a200tsbg484-1. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command. Check if board.repoPaths pa
  8. Okay! Currently, I have working example and can write data and read data using the MIG7 interfaced together with a uB. However, since this is a soft core and runs with a certain speed , we wont get maximum speed here. I might be wrong and just want clarifications. regards, John
  9. Hello! I have been investigating how multiple clock domains work and how you can send data ASAP from a camera module to a SDRAM (taking a pic). I am currently using a Nexys-Video and a Zed board and wonder if I could get some tips. The problems I encountered during my research is: -The picture I take has to be stored ASAP, meaning I have to use the mig7 interface for the SDRAM and HDL code. However this will be hard since it requires me to understand how the MIG7 works and thus writing a HDL that is adjusted to work with it. - What is the maximum f