Shuvo Sarkar

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  1. Hi @hamster, I have seen in SDSoC-platforms example the grayscale is applied, which takes rgb and weighted with graysale values. The code I found is following. Will it work in the hdmi in and vga out project sdk? void DemoGrayFrameSw(u16 *srcFrame, u16 *destFrame) { u32 xcoi, ycoi; for(ycoi = 0; ycoi < DEMO_HEIGHT; ycoi++) { for(xcoi = 0; xcoi < DEMO_WIDTH; xcoi++) { u16 r, g,
  2. Dear experts, I have been working with the zybo hdmi in vga out project. Normally, It takes 24 bit vga signal, but I want to feed 16 bit grayscale as input (YUV 4.2.2) through vid in to AXI-4 Stream and 16 bit grayscale as output. Is there any solution for this? thanks- Shuvo
  3. Hi @jpeyron, thanks a lot it finally worked. First, I have set the laptop resolution 1280x720p and then set also option 3 in Tera Term. Thanks a lot- Shuvo
  4. Hi @jpeyron No. But, option 8 will only grab a frame and I need video streaming. I want to do it from option 1. Thank you, Shuvo
  5. Hi @jpeyron I set 1280x720 at laptop but at the VGA this change has no effect.
  6. Hi @JColvin This is what I am currently getting. At the monitor settings it shows input is VGA [email protected] I unplugged and plugged the VGA cable.
  7. Hi @jpeyron, when I select [email protected], It gives me bigger image and a part of the whole frame is displayed. It only gives perfect frame at 1080p settings. What did you mean by re-reacquiring? could please explain it. thank you- Shuvo
  8. Dear Experts, The hdmi in to vga out demo project gives perfect resolution at 1080p settings. But, wherever I try to set other resolution as I need 720p, it gives me extended resolution. Is there any option that I can fix it at 720p? Coz the monitor I want to use for output doesn't support Full HD (1080p) resolution. https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-hdmi-demo/start Regards- Shuvo
  9. Dear Experts, I want to implement XAPP1167 OpenCV HLS Xilinx project which mainly shows the edge at the output video. In the ZYBO hdmi demo project, I have added this custom IP between the interface of video in and AXI4 stream to VDMA. Initially, I got the error message says, "Bus interface property TDATA_NUM_BYTES does not match". Then I added axis_subset_converter_0 which allows me to downgrades TDATA width from 3 to 2 byte and successfully validated the updated designed. I also able to generate bit stream but the design does not fulfil the timing requirements. I am getting total negati
  10. Hi @Jon, It just worked in Vivado 2016.2. I don't know why it wasn't work in 2016.4. Thanks again for all the support. Shuvo
  11. Hi @Jon, Yes, I can able to create other project using Zybo board. Here is the screen shorts and report. Report.txt
  12. Hi @Jon, I wish it also work for me. Implementation_error.txt
  13. Hi @jon & @Arthur, I just have formatted my operating system and tried to re-synthesis the Zybo Video demo. But, this I got stuck into a new problem. The project shows some errors and stop executing. I am using Vivado 16.4 and also added the library files, board files into the directory . May there are some mistake that, I could not find. Would you please have a look and direct me the right way. Hi @Jon, The design is working till Synthesis. Only the error massage is showing during Implementation. Could you link me the latest version of hdmi project and the li
  14. Hi @jon & @Arthur, I just have formatted my operating system and tried to re-synthesis the Zybo Video demo. But, this I got stuck into a new problem. The project shows some errors and stop executing. I am using Vivado 16.4 and also added the library files, board files into the directory . May there are some mistake that, I could not find. Would you please have a look and direct me the right way.