• Content Count

  • Joined

  • Last visited

About Hayder

  • Rank

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. Hi @Allan I think this file is what you search for https://www.sendspace.com/file/iuhlqt
  2. Hi @Allan I did that project already, let me try to upload it .... just wait.... I have bad net speed
  3. Hi I did it at last, thank you for your help.
  4. Hi @Allan You need to install Zybo files into Vivado, Here, ( this is for Vivado 2015 and later)... also I made simple project for making blinking LEDs, using Verilog language, but not using IP block.
  5. Hello @jpeyron I wrote simple Verilog for displaying just one number module one( output [1:0] ja_p, output [6:0] jb_p ); assign ja_p = 2'b0; assign jb_p = 7'b1111100; endmodule But I got strange char as in the attached picture !! I connected my Display as: A- 11 B- 7 C- 4 D- 2 E- 1 F- 10 G- 5 And when I remove one wire , the corresponding segment went off so I think the wiring is OK... Thanks again for help
  6. Hi @jpeyron There are no errors in Vivado, the 7 segment display rubbish char... After searching I found that my 7 segment is common cathode not common Anode, so please how can change the programming according to ? just reverse lines 53,59,65 ja_p = 4'b0111; ------> ja_p = 4'1000; ? also reverse LED_BCD bits? Thanks again
  7. Hello This is the second project for me in FPGA for fun. I want to connect external board with 7 seg as a counter, so I put this Verilog code with this XDC file but the output is something error , could you please figure it out? I use common Anode display PMOD XADC pin 1 ---> pin 12 (7 Seg) pin 2 ----> Pin 9 pin 3 ---> Pin 8 pin 4 -----> pin 6 ------------------------ PMOD JB pin 1 ---> pin 11 pin 2----> pin 7 pin 3-----> pin 4 pin 4 ----> pin 2 pin 5 ----> pin 1 pin 6 ---> pin 10
  8. Hello @jpeyron in the book, the author uses Opal Kelly XEM6002. for the project which is module BLinkLED_Sys2( input CLOCK_IN, input RESET, output OUT_HIGH, output OUT_LOW ); //-----Internal Variables----- reg[31:0]blinkcount; //---- internal signals wire clk_in; wire reset_in; //------Code Starts Here------ assign clk_in = CLOCK_IN; assign reset_in = RESET; assign OUT_HIGH = blinkcount[21]; assign OUT_LOW = blinkcount[20]; always @(posedge clk_in) if (reset_in) begin blinkcount <= 32'b0; end else begin blinkcount <= b
  9. Thanks Jon I understand that the version of Xilinx is outdated, but he uses it in the book. Now just I want to know to find the ports of Ground , RESET, BUSES AND CLOCK of Zybo! thanks again
  10. Hello I'm newbie to FPGA, and start with ISE 14.7 , Zybo z7 and Make FPGA book by David Romano the first example is make Frequency divider. now I reach how to connect the virtual program to real I/O ports, but I find a lot of difficulties to put this into my board using PlanAhead 14.7 how to find these port in Zybo - clock - reset - [31:0] bus output with just 2 bits bus tap. - Voltage thank you for your help