Michele

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About Michele

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  • Birthday 11/06/82

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    Turin Italy
  1. [SOLVED] Zybo USB OTG - Reset via MIO 46

    Hi, finally I have solved in this way: - I have modified the system-top-dts adding: usb_phy0: phy0 { #phy-cells = <0>; compatible = "usb-nop-xceiv"; reset-gpios = <&gpio0 46 1>; }; - I have also modified the pcw.dtsi in this way: &usb0 { status = "okay"; dr_mode = "host"; usb-phy = <&usb_phy0>; Attached the result. My usb key now is correctly detected and also the two partitions on it has been corectly detected into /dev. Thx again I hope this can be useful for others that have same problem. Michele
  2. Hi, I'm trying to set up the USB OTG on Zybo board. I've done the following: 1. Checked the "Peripherals I/O pin" field for the USB0 and MIO as well for reset the PHY chip into Re-customize IP ( double click on zynq ).It matched with the schematics. 2. I have checked the devicetree auto-generated by SDK ( 2017.2 ).I have attached it. Seems to be good. 3. I have plugged my usb key on J10 ( the bigger USB connector ) as I want zybo to be a host controller. 4. The jumper JP1 is shorted. 5. The MIO 46 have to provide the reset signal to the PHY chip if I understand correctly 6. The connection between zynq ps and PHY is ULPI ( 12 signals from MIO 28 to 39 ) 7. When I boot the whole thing the device driver is correctly registered ( dmesg | grep usb ) but my usb key is not recognized. 8 If i stop the u-boot autoboot and issue the followings: - usb info ---> says that the usb is stopped - usb reset --> it rescan and detect correctly the host conroller and the usb key - boot --> boot the whole thing but the usb key is not recognized. I have searched a lot and, if I understand well, the following line on devicetree: usb-reset = <&gpio0 46 0>; declare that the gpio 46 have to became the reset signal for PHY chip ( active low , I have checked on Vivado into re-customize ip menu ) and in fact the "usb reset" on u-boot shell works but I don't know why I cannot recognize my usb key. I have also read that the fsbl have to issue the reset signal. I have done a search on fsbl source code and I have not found any USB reset function or something similar. The only thing that I have found is into ps7_init.c but honestly I can't understand a lot of that code... Anyone have encountered the same problem?? I have read that many peaple had problems with zybo USB OTG. I have also tried to do this into u32 FsblHookBeforeHandoff(void) but it doesn't boot ( maybe my mistake I have to retry ). Thanks in advance. Michele pcw.dtsi system-top.dts zynq-7000.dtsi
  3. Hi, some good news, I have followed your suggestion and I have also removed the PHY part of devicetree that I have added and now it works!! Maybe as described on "ZYBO FPGA Board Reference Manual" : "Although the default power-up configuration of the PHY might be enough in most applications, the MDIO bus is available for management." so maybe it is not really necessary the PHY level in fact I can see from boot log that the RTL8211E will be automatically recognized. Thanks again, with this problem I have understood many things about devicetree and other things. Michele
  4. Hi, really thanks a lot for your suggestion and sorry for late reply. Now I have re-generated the bitstream and exported to SDK the hdf file, created the fsbl. Now I have to restart to compile the whole other stuffs but I'm pretty sure that with the modification you have suggested it could work. So thx again. Now I have clarified to myself the role of RGMII, MDIO and MAC to PHY connection. I'll keep you informed. Thanks again!! Michele.
  5. Hi, I'm trying to boot a linux OS ( Ubuntu core armhf ) on Zybo board. I have done the following steps: 1. Create a project in Vivado 2017.2, a project consist of a Zynq and just one custom IP core, a led controller just to turn on and of the 4 leds on board. 2. I have successfully generated the bitstream and exported the hdf in SDK. 3. In SDK I have created a project for build the fsbl successfully 4. I have built u-boot ( git clone from xilinx repo on github ) just changing the zynq_common.h file to load just the kernel and the devicetree ( not the uramdisk because I would like to put the rootfs on sd card 2nd partition ) 5. I have built the kernel ( always from xilinx github ) using the zybo_zynq_defconfig as configuration and I have successfully generated the uImage 6. I have prepared a ubuntucorearmhf rootfs 7. I have packaged into BOOT.BIN file the fsbl, bitstream and u-boot 8. I have used the devicetree generator from xilinx github to generate my devicetree ( files attached ), with modified bootargs properly ( I hope ) 9. As you can see there is no PHY into pcw.dtsi or zynq-7000.dtsi so I have added that into a file called ethernet.dts ( made by me ) including the system-top.dts just to leave the auto-generated devicetree without modification. 10. I put the BOOT.BIN , uImage and devicetree.dtb ( compilation of ethernet.dts ) into the 1st partition of my sdcard, the rootfs into 2nd 11. At boot time the system boots without problem but it says that there is no PHY for ethernet and if I do an ifconfig the eth0 interface is absent. I have done a mistake on binding the PHY for realtek ethernet controller?? Another step I have tried is to use the BOOT.BIN and the image.ub provided by Digilent on zybo bsp 2015.4 (Digilent-Zybo-Linux-BD-v2015.4) and like this the PHY has been found and I can see the eth0 interface. I have also tried to understand the difference between my devicetree and the Petalinux one ( see .txt file ) without success. I have tried to use your zybo_base_system project instead of a clean project from scratch with same results. I have finally tried this https://github.com/MarioLizanaC/Linaro-O.S.-for-Zybo/ , a project found on github where a guy boot Linaro ( I have done it with Ubuntu core ) using as start I think your zybo_base_system but with 3.18 kernel instead of 4.9 kernel and Vivado 2015.4 instead of Vivado 2017.2 . Thanks in advance. Michele ethernet.dts pcw.dtsi system-top.dts zynq-7000.dtsi gem0_node_petalinux_bsp.txt