Michele

Members
  • Content Count

    5
  • Joined

  • Last visited

About Michele

  • Rank
    Newbie
  • Birthday 11/06/1982

Profile Information

  • Gender
    Male
  • Location
    Turin Italy

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. Hi, finally I have solved in this way: - I have modified the system-top-dts adding: usb_phy0: phy0 { #phy-cells = <0>; compatible = "usb-nop-xceiv"; reset-gpios = <&gpio0 46 1>; }; - I have also modified the pcw.dtsi in this way: &usb0 { status = "okay"; dr_mode = "host"; usb-phy = <&usb_phy0>; Attached the result. My usb key now is correctly detected and also the two partitions on it has been corectly detected into /dev. Thx again I hope this can be useful for others
  2. Hi, I'm trying to set up the USB OTG on Zybo board. I've done the following: 1. Checked the "Peripherals I/O pin" field for the USB0 and MIO as well for reset the PHY chip into Re-customize IP ( double click on zynq ).It matched with the schematics. 2. I have checked the devicetree auto-generated by SDK ( 2017.2 ).I have attached it. Seems to be good. 3. I have plugged my usb key on J10 ( the bigger USB connector ) as I want zybo to be a host controller. 4. The jumper JP1 is shorted. 5. The MIO 46 have to provide the reset signal to the PHY chip if I understa
  3. Hi, some good news, I have followed your suggestion and I have also removed the PHY part of devicetree that I have added and now it works!! Maybe as described on "ZYBO FPGA Board Reference Manual" : "Although the default power-up configuration of the PHY might be enough in most applications, the MDIO bus is available for management." so maybe it is not really necessary the PHY level in fact I can see from boot log that the RTL8211E will be automatically recognized. Thanks again, with this problem I have understood many things about devicetree and other things.
  4. Hi, really thanks a lot for your suggestion and sorry for late reply. Now I have re-generated the bitstream and exported to SDK the hdf file, created the fsbl. Now I have to restart to compile the whole other stuffs but I'm pretty sure that with the modification you have suggested it could work. So thx again. Now I have clarified to myself the role of RGMII, MDIO and MAC to PHY connection. I'll keep you informed. Thanks again!! Michele.
  5. Hi, I'm trying to boot a linux OS ( Ubuntu core armhf ) on Zybo board. I have done the following steps: 1. Create a project in Vivado 2017.2, a project consist of a Zynq and just one custom IP core, a led controller just to turn on and of the 4 leds on board. 2. I have successfully generated the bitstream and exported the hdf in SDK. 3. In SDK I have created a project for build the fsbl successfully 4. I have built u-boot ( git clone from xilinx repo on github ) just changing the zynq_common.h file to load just the kernel and the devicetree ( not the uramdisk beca