I think I have all the pin constraints correct. Unfortunately, my IP is RMII so that Xilinx MII to RMII IP won't work. I would need a RMII to MII IP. I guess I'll move forward with my application and see if it works.
Is there anything physically preventing me from putting the PHY on the Arty board in RMII mode? I'm generating a 50MHz eth ref clock using an MMCM , I'm driving the MII_MODE (G16) pin high to strap it to RMII. What else do I need to do?
My personal interest in FPGA development includes the effort to learn VHDL.
I look forward to this. I had purchased a S3 Starter Board specifically to go through Pong Chu's "FPGA prototyping by VHDL examples" book.
I'm interested in purchasing the voucher for a node locked license of SDSoC. The description says it's locked to the Zedboard and Zybo. Is it locked to those particular boards or would the license work for the PYNQ and Arty Z7?