bkzshabbaz

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About bkzshabbaz

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  1. I think I have all the pin constraints correct. Unfortunately, my IP is RMII so that Xilinx MII to RMII IP won't work. I would need a RMII to MII IP. I guess I'll move forward with my application and see if it works.
  2. bkzshabbaz

    FPGA

    Kind of defeats the purpose of these message boards if you post an issue, get it resolved, and remove the question and resolution, no?
  3. Did you build the design from source? Or did you use the pre-built images from Analog Devices?
  4. bkzshabbaz

    Arty Board with RMII?

    Is there anything physically preventing me from putting the PHY on the Arty board in RMII mode? I'm generating a 50MHz eth ref clock using an MMCM , I'm driving the MII_MODE (G16) pin high to strap it to RMII. What else do I need to do?
  5. I think I've figured out the problem. I had to enable interrupts in the PS. The interrupts are enabled in PS-PL Configuration -> General -> Interrupts -> PS to PL -> SPI
  6. Did you ever get a resolution to this either by yourself or from Xilinx support? I'm running into the same issue as you.
  7. I'm running in to this same issue. Is there a resolution?
  8. What bootargs did you use to resolve this?
  9. If you think 5-6 minutes is painful, our design takes 60+ minutes. 😥
  10. My personal interest in FPGA development includes the effort to learn VHDL. I look forward to this. I had purchased a S3 Starter Board specifically to go through Pong Chu's "FPGA prototyping by VHDL examples" book.
  11. I would be interested in this...
  12. I have a PYNQ, can I buy the Zybo Accessories Kit and use the voucher for the PYNQ?
  13. I'm interested in purchasing the voucher for a node locked license of SDSoC. The description says it's locked to the Zedboard and Zybo. Is it locked to those particular boards or would the license work for the PYNQ and Arty Z7?