boyerkg

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  1. Hi All, I have the ethernet echo server running on the Nexys Video board (artix 7 200t fpga). Ultimately, this Microblaze design utilizes too many resources. I was wondering if anyone out there has a lite weight state machine solution to controlling the Xilinx Mac for IP address and Mac address and framing? By the time you add extra scatter gather DMA to the DDR and Microblaze system, so you can fifo data from say an ADC to the ethernet mac, these add significant resources. Any thoughts? Keith
  2. OvidiuD, Please disregard my issue. I had a flag set incorrectly in the bsp settings. It was choosing the wrong lwip library. Keith OvidiuD, Please disregard my issue. I had a flag set incorrectly in the bsp settings. It was choosing the wrong lwip library. Keith
  3. OvidiuD, Thanks for the update on the Realtek repository. I am getting the Warning that the PHY is not Marvell or TI, also. I am also getting the link to be up then it drops down. For a short time a ping will get through. I downloaded your GIT repository and followed the bsp update, as you suggested, and I still get the error. Any ideas. I am on the nexys video board. Keith
  4. Hi Jon, I want to re-load a new FPGA image into the flash after the original design has been loaded into flash. The original flash will be loaded using Xilinx Vivado and their flash load hardware. Essentially, I want to take over the Xilinx hardware and load a .mcs bit file through our user data path to program flash. After reset, this new image will be loaded in the usual way from flash to the Artix-7 fpga. Keith
  5. Hi All, I was wondering if anyone has successfully implemented a post configuration quad SPI flash Xilinx programming without micro processor? I am using the Xilinx Artix-7, and I want to reprogram a new .mcs file into flash using an existing data path: not the Xilinx tools. I would also like to know how to connect to the existing SPI flash pins. I instantiated the axi_quad_spi IP, and it doesn't show how to simply us it. The Xilinx project seems incomplete. Any help would be appreciated. Keith
  6. Jon, What about the project that is shipped with the Nexys Video board? It has the temperature and internal voltages displayed on the LCD readout. It is probably more like what we are doing. The project that you mention has EOC hooked to DEN. I am not getting EOC for some reason. xadc_wiz_0 XADC ( .daddr_in(xadc_addr), .dclk_in(CLK100MHZ), .den_in(enable), .di_in(), .dwe_in(), .busy_out(), .vauxp0(xa_p[1]), .vauxn0(xa_n[1]), .vauxp1(xa_p[0]), .vauxn1(xa_n
  7. Hi All, We are having trouble with our XADC on the nexys video board. We have a DDR3 design that has a XADC instantiated with convert frequency set to the requirements of the DDR3 MIG. The 12 bit temp output of the XADC is routed to the MIG. Our issue is that we always get zero output from the XADC temp vector. We have simulated the design using the verilog code from the Xilinx ug480_7Series_XADC document. In simulation we see drdy response from the XADC, but the data is always zero. It is set in the simulation text file to 63 C. Another funny thing is that we never see the EOC
  8. Thanks Dan and ELODG, I took the third option, which made the most sense moving forward. I implemented a 2x MMCM, to get the 200Mhz. I recompiled the MIG to 400Mhz and 200Mhz input, with no buffer sys clock and use system clock for the ref. The MIG PLL must not have been locking. It works fine now. Thanks again. It is nice that you all have been responsive to my questions. Regards, Keith
  9. Dan, I used 100Mhz as the input clock and I used nobuffer for both the input and reference clock. I got the following error in bitstream generation: ERROR: [DRC REQP-79] connects_REFCLK: u_mig_7series_0/u_mig_7series_0_mig/u_iodelay_ctrl/u_idelayctrl_200: The IDELAYCTRL REFCLK pin should be connected It is not hooking put he refclk. If I use a 200Mhz clock selection, the refclk gui lets me select 'use system clock'. I compared my mig_a.prj file to yours, and they are identicle? Keith
  10. Thanks Dan. Like I said, the first issue was that I wasn't getting the DDR reset to the memory part to go out of reset. I was seeing the PLL change to the 200Mhz after I released the sys_reset. I was thinking that I didn't have something constrained correctly. So, I added a 100Mhz constraint to the input sys_clk. That made the MMCM Pll VCO unhappy in Vivado. Vivado MIG IP only lets you select from 330Mhz to 400Mhz. If I select the input clock to be 200Mhz, it is unhappy with the constraint for the sys_clk?? I will look at your ucf. Have a good weekend, Keith
  11. Thanks All, The design is a combination of vhdl and verilog. I have a simulation running that works. I have confirmed that I have the DDR3 p and n clocks running and responding to the resetn. I am not getting the DDR3_resetn to go inactive. The DDR3 clock is at 200Mhz, with the ref clock coming in from "sysclk" at 100Mhz. The MIG 7 design states 400Mhz. I don't know how it would know the difference, but I'm pretty sure one needs the reset to go away. I just checked the pin list for the reset, and it matches the digilent nexys video schematic. Keith
  12. H All, So, I am trying to get a DDR3 test running on the Nexys Video board was to have one of the example designs that had a mig 7 controller for this board generate an example project. The example project creates a memory traffic controller. This is a Xilinx generated module/example. I used that project to update the pin list for the Nexys Video board pins, for everything from the system clock and reset to the compare error output and init calibration complete and of course the DDR3 pins. I checked the pin list, and everything seems to be hooked up according to the video boar
  13. Hi Dan and Arthur, So, what I ended up doing to get a DDR3 test running on the Nexys Video board was to have one of the example designs that had a mig 7 controller for this board generate an example project. The example project creates a memory traffic controller. This is a Xilinx generated module/example. I used that project to update the pin list for the Nexys Video board pins, for everything from the system clock and reset to the compare error output and init calibration complete. I checked the pin list, and everything seems to be hooked up according to the video board sche
  14. Dan, When I get to the point in the MIG generation to select the pins, Vivado gives an error 7. It simply exits the IP generation. The Xilinx forums discuss this issue, but there appears to be no resolution. Really???? Keith