BogdanVanca

Technical Forum Moderator
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  1. Like
    BogdanVanca got a reaction from shantaramj in 'mipi_csi2_rx_top' has undefined contents and is considered a black box   
    Hello @shantaramj,
    The IP has it's own constraints and set-ups that would fail if you reset them in a different Vivado Version. Please use the recommended version of Vivado for this project, go trough syntesys, implementation and generate bitstream. If everything works as expected you can open the project in 2018.2, but please make sure that you don't reset the output products for this ip. If you need although to go trough a reset, please lock the ip before doing that.
     
    Best Regards,
    Bogdan Vanca 
      
  2. Like
    BogdanVanca got a reaction from lowena in How can I passthrough data from FPGA to PC with USB UART on the PS?   
    Hello,
    First, As you may think you have to write your own UART vhdl/verilog module,  with an RS323 interface. After you make sure that it works correctly, you have to add to your code and axi lite interface.  There are two ways for doing that:
    1. You add it by your own, and keep your code as a module. 
    2. Package your module as an custom ip and use the template given by Xilinx. 
    Personally, I will probably go with the second option. And that is because, the template is clearly written and commented. Inside this template there is a state machine that gives you access to a couple of registers.Trough these registers you can pass data from PL to PS side. After you have your own IP, you can add it into a block design and connect it trough the AXI Interconnect. On this stage your IP will have it's own address into the address editor. With that, you can access trough the lite interface each individual register.  
     
    Best Regards,
    Bogdan Vanca 
     
  3. Like
    BogdanVanca got a reaction from giamico in Basys 3 HW Target shutdown (Vivado)   
    Hi @giamico,
     
    This happens when you lose the connection with the Board. Please try on with a different USB cable.
  4. Like
    BogdanVanca got a reaction from bitslip in Setting the Pcam 5C's internal registers   
    Hello @bitslip,
    Yes, you are correct. Theoretically you can rescale the image at any size, even at 1000x1. I'm saying theoretically because I never tried it, not because I think it's not possible. The sensor doesn't have any kind of constraints  that could stop you to do that. Or, at least I couldn't find any into the datasheet.  The VDMA has to have a fix number of bytes for each individual transfer. So, if you are playing with the number of bytes, you have to reinitialize the function above for each transfer, as it was done in the DEMO. 
  5. Like
    BogdanVanca got a reaction from bitslip in Setting the Pcam 5C's internal registers   
    @bitslip
     
    To answer your questions.
    1. Yes. You can can output any image size that is described into the sensor datasheet. This can be done on the fly if you reprogram the right registers. Part of this is already achieved by the demo project. The change resolution option from the user interface reprograms the sensor for each resolution. For more info you can dig into the fallowing function: pipeline_mode_change(vdma_driver, cam, vid, Resolution::R1280_720_60_PP, OV5640_cfg::mode_t::MODE_720P_1280_720_60fps);  The OV5640_cfg namespace has 3 different modes for each individual resolution. Each mode is correspondent to a structure that stores all the registers values needed for that resolution. To be more specific, all the registers that are responsible for image windowing (0x3800 to 0x3807), are configured in these structures. Let's take for example the cfg_1080p_15fps_ structure. If you want to calculate the output X size, you would have 2287(0x3804, 0x3805 registers) - 336(0x3800, 0x3801) - 16(0x3810, 0x3811) which is equal with 1919. The registers 0x3808 and 0x3809 are configured for 1920, so the image is basically un-scaled. For image windowing you have to rewrite those registers. 
    2. Yes and No. It depends on how many resolution do you want to add. Unfortunately I cannot give you a number, because I'm not sure how versatile is the current design. For now it works for 3 different resolution, but is hard to tell how many you could add on. Each individual resolution may have a different pixel clock, or as I said before, a different set of image constants. 
     For now, I would probably start to understand how to configure the above registers, and I would start playing with them. You also need to make sure, that the vdma transfer works as expected. As you may see, the pipeline_mode_change function reconfigure the vdma_driver object for each resolution. 
  6. Like
    BogdanVanca got a reaction from Bianca in Setting the Pcam 5C's internal registers   
    Hello @bitslip,
    Things are a little bit more complicated.  Indeed, for changing the resolution you have to rewrite some registers. But you also need to make sure that the Video Trimming controller ip generates the required constants for you resolution. I wouldn't recommend to write all the needed registers from the control interface (it would be agonising) Instead I would go with the existent logic for changing the resolution, which is adding a new structure with all the register values. As an example, you can check the OV5640.H file. I much simple and quicker solution would be to use our video scaller ip. This ip was written in HLS and it was used in the  fmc pcam adapter demo for re-scalling the video at a 640x480 resolution.  You can check the design in here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zedboard-fmc-pcam-adapter-demo/start
     
    Best Regards,
    Bogdan Vanca 
     
  7. Like
    BogdanVanca got a reaction from bitslip in Setting the Pcam 5C's internal registers   
    Hello @bitslip,
    Things are a little bit more complicated.  Indeed, for changing the resolution you have to rewrite some registers. But you also need to make sure that the Video Trimming controller ip generates the required constants for you resolution. I wouldn't recommend to write all the needed registers from the control interface (it would be agonising) Instead I would go with the existent logic for changing the resolution, which is adding a new structure with all the register values. As an example, you can check the OV5640.H file. I much simple and quicker solution would be to use our video scaller ip. This ip was written in HLS and it was used in the  fmc pcam adapter demo for re-scalling the video at a 640x480 resolution.  You can check the design in here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zedboard-fmc-pcam-adapter-demo/start
     
    Best Regards,
    Bogdan Vanca 
     
  8. Like
    BogdanVanca got a reaction from learni07 in Tera Term displays [ brackets continuously with Zybo 7z020   
    Hi @learni07,
    Can you please check the baud rate from Tera-Term? For this, click on Setup->Serial port and check Baud Rate down-menu. It has to be 115200.
    Best Regards,
     Bogdan Vanca
  9. Like
    BogdanVanca reacted to Ciprian in Digital Twin   
    Hi @Kris Persyn,
    It depends on how you manage your resources, driving immersive visuals on a HDMI display can be done in multiple ways at different resolutions, some are PL taxing others are DDR taxing; you could generate entire frame buffers in PL or PS or you could find a optimal algorithm to change just the previous frame or you could allocate a high number of frame buffers and then run them in a loop.
    It also depends on how math lab synthesizes the IP you will need to add to your design.
    If you design your project properly and don't aim for a resolution higher more 720p( I'm being conservative, we managed to drive the HDMI at 1080p with processing filters without a problem)  I think it should be enough for what you want to do, resource wise.
    My suggestion, download and install Vivado, download and install the board files, create and implement your project look at the resource consumption and then buy a board.
    - Ciprian
  10. Like
    BogdanVanca got a reaction from Blake in How to launch Digilent hdmi FMC with zc702 board   
    Hi @Blake
    Sorry for my late reply. Please check the fallowing link: https://www.dropbox.com/s/87cm0faa66sdra9/fmc_hdmi_in_1.zip?dl=0 This is the first variant of the project. I will try to make new updates into the close future. The project reads on HDMI1 IN input the resolution given by HDMI OUT, so you have to make a loop-back between those two. For patterns I used the test pattern generator from Xilinx, which needs a license, although the license is free. So, you either request one from Xilinx, or you can try to copy the one that I have. Check the attached document. You have to copy the file on this location : C:\Users\<your username>\AppData\Roaming\XilinxLicense. I will keep you in touch every time I add something new. If you have any questions please fell free to ask.
    Best Regards,
    Bogdan Vanca  
    tpg.zip
  11. Like
    BogdanVanca got a reaction from Blake in How to launch Digilent hdmi FMC with zc702 board   
    Hi  @Blake,
     
    Short update. I've recreated Adam project with a different setup and it works. I'm able to read different resolutions trough the first input of the FMC-HDMI adapter. I'm using a zybo to generate those resolutions, which further on are read by the VTC ip core. Check the images bellow:
    The first image is the serial terminal from which I communicate with Zybo, and the second image shows the output values within the VTC ip core. 

     
    I couldn't be able the replicate this using a laptop as an hdmi source, and that is because I think there are problems with the edid file used by Adam in his project. For now,  you can use his project as reference, and for future I will try to get rid off Zybo and add everything into Zed. Also if you check this link: https://forums.xilinx.com/t5/Xcell-Daily-Blog-Archived/Adam-Taylor-s-MicroZed-Chronicles-Part-216-Capturing-the-HDMI/ba-p/794874 you will found out that : "Initially in its free-running mode, the ADV7611 outputs video in 480x640 pixel format. Checking the VTC registers, it is also possible to observe that the detector has locked with the incoming sync signals and has detected the mode correctly, as shown in the image below: " So the message that you initially received is actually correct. I will keep you in touch with everything that I'm adding to this project. 
    Best Regards,
    Bogdan Vanca 
  12. Like
    BogdanVanca reacted to Ionut in Zybo Z7-20 PCAM Demo Unimplementable on Vivado 2017.4   
    You're welcome!
    I am glad it is working. Yes, this thread should help others trying to run the Pcam 5C demo on Zybo Z7.
    Best Regards,
    Ionut.
  13. Like
    BogdanVanca got a reaction from Bianca in How to launch Digilent hdmi FMC with zc702 board   
    Hello @Blake,
    I've created for you an image that test your FMC-HDMI adapter. It does a basic data transfer between the HDMI output of the ZedBoard and both of the adapter hdmi inputs. Prior to this it also uses all the I2C lines. Please check the .rar attached file. In order to recreate the test, please fallow the fallowing steps:
    1.Make sure that you have everything in place, check the bellow instructions and the first image.
    Connect USB cable from PC to ZED USB PROG port (J17) Connect USB cable from PC to ZED UART port (J14) Connect FMC-HDMI board to FMC connector J1 (of ZED) Connect Power cable to J20 (of ZED) Set mode jumpers for JTAG programming (all to GND) Set J18 (of ZED) jumpers to 3V3 or 2V5. I'v tested both variants. Create a loop between HDMI-OUT J9(ZED) and FMC-HDMI IN1 of the adapter. Turn ZED board on 2. Open Vivado (I used Vivado 2017.4).
    Open Vivado, and click on Open Hardware Manager within the Welcome Page. After this click on Auto-Connect. You should see the Zed into the upper left panel.Check the image bellow.
    3. Add Configuration Memory Device
    Right click on xc7z020_1 and choose "Add Configuration Memory Device". Check image bellow. 4. Choose the right memory device for ZED. 
    Please choose "s25fl256s-3.3v-qspi-x1-dual_stacked" from the list. Click to program the device. Check images bellow.  
     5.Program the device with the files attached to this message.
    For "Configuration file" you choose BOOT.bin. For "Zynq Fsbl" you choose fsbl.elf.  Click OK.
    6. Wait until it gets programmed. After finish, you click OK. 
    7. Prepare the board for testing. 
    Open a serial terminal, termite, putty, teraterm etc. Find the COM port and choose 115200 for baud rate. Set jumpers for QSPI programming (MIO5 on 3V3 and SIG, the others on 3V3 and GND). Power OFF the Board. Power ON  the Board.  The image should boot. See the image bellow.  
    8.Do the actually test.
    Make sure that the HDMI-OUT (ZED) is connected to HDMI-IN1 of the FMC-HDMI adapter.  Press ENTER. Wait for the test to finalize. 
    Make sure that the HDMI-OUT (ZED) is connected to HDMI-IN2 of the FMC-HDMI adapter. Make sure that your adapter is not loose.  Press ENTER. Wait for the test to finalize. 9.Check the results, and give me an update  .
     
    image.rar
  14. Like
    BogdanVanca got a reaction from Bui Cuong in IP is locked and cannot be customized   
    Hello @Bui Cuong,
    Please attach to your message the zip archive of both projects. You can try to update all the IP's, and after that to generate the output products.  See if this gives you a solution. Thank you. 
    Best Regards,
    Bogdan Vanca  
  15. Like
    BogdanVanca got a reaction from HelplessGuy in Looking for the right board   
    Hello @HelplessGuy,
    Zybo-Z7 will satisfy your needs. It has an Ethernet connector and also an On-chip analog-to-digital converter (XADC). When you say "160kHz" you probably refer to the sample frequency. The on board analog to digital converter has an sampling rate of 1MSPS and 16 different aux channels. 
    You could also look on Arty Z7-10/20 version (https://store.digilentinc.com/arty-z7-apsoc-zynq-7000-development-board-for-makers-and-hobbyists/), or even ZedBoard(https://store.digilentinc.com/zedboard-zynq-7000-arm-fpga-soc-development-board/). Or if you want to work with an FPGA based board, you can go with Arty-A7(https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/) or Nexys4 (https://store.digilentinc.com/nexys-4-artix-7-fpga-trainer-board-limited-time-see-nexys4-ddr/). I also depends on how much money do you want to spend.
    Best Regards,
    Bogdan Vanca 
  16. Like
    BogdanVanca got a reaction from Ram in DRAM or ON-CHIP-MEMORY   
    Hello @Ram,
    In SDK, there is an linker script file that specifies where different sections of an executable are placed in memory. Please check "lscript.ld".  All of those sections are user-configurable.  
     
    For all of our projects we use the "ps7_ddr_0" memory section.
    Best Regards,
    Bogdan Vanca
  17. Like
    BogdanVanca got a reaction from JColvin in Basys 3 XADC   
    Hello @Rohit kumar jain,
    Yes it is possible. The on board xadc has 16 different aux analog inputs.
    Best Regards,
    Bogdan Vanca 
  18. Like
    BogdanVanca got a reaction from JColvin in BASYS3 board - XADC ports   
    Hello @donwazonesko,
    Please check this document : https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf for more info.
    "- what's the sampling rate (i think its 1 Mpsp)?"
    The sampling rate is indeed 1 MSPS. 
    "- what's the delay between ports ?"
    Can you please be more specific ?. Are you referring to the delay between conversions ? If yes, 26 ADCCLK cycles are required to acquire an analog signal and perform a conversion. This implies a maximum ADCCLK frequency of 26 MHz.
    "- is it compatible with microphone output (diff or single ended)?"
    Probably yes. But you have to make sure that the microphone output doesn't exceeds 500 mV for bipolar mode and 1 V for unipolar mode . 
    For more info, please check this document : https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf.
    Best Regards,
    Bogdan Vanca 
     
  19. Like
    BogdanVanca reacted to jpeyron in Basys 3 XADC   
    Hi @Rohit kumar jain,
    To add to @BogdanVanca's post , here is an XADC demo for the Basys 3 that uses 4 analog inputs. Here is the GitHub releases for the XADC demo.
    thank you,
    Jon
     
     
     
  20. Like
    BogdanVanca reacted to awang735 in PMOD DA1 to zedboard   
    Nevermind, i downloaded the digilent board files from https://reference.digilentinc.com/learn/software/tutorials/vivado-board-files/start?redirect=1 and was able to connect the pmod ip via the board tab in ip integrator like it says in the walkthrough
  21. Like
    BogdanVanca got a reaction from Ram in programming guide of zynq   
    Hello @Ram,
    Please check this link : https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq-server/start "This guide will provide a step by step walk-through of creating a Zynq based hardware design using the Vivado IP Integrator that will build over the Getting Started with Zynqguide by making use of the on-board Ethernet port and GPIOs for the Zybo FPGA board.". You can start from here, and use the same hardware logic but different type of application for uart, spi etc. 
    Best Regards,
    Bogdan Vanca
  22. Like
    BogdanVanca got a reaction from JColvin in programming guide of zynq   
    Hello @Ram,
    Please check this link : https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq-server/start "This guide will provide a step by step walk-through of creating a Zynq based hardware design using the Vivado IP Integrator that will build over the Getting Started with Zynqguide by making use of the on-board Ethernet port and GPIOs for the Zybo FPGA board.". You can start from here, and use the same hardware logic but different type of application for uart, spi etc. 
    Best Regards,
    Bogdan Vanca
  23. Like
    BogdanVanca got a reaction from JColvin in issue with xadc header auxiliary input   
    Hello @farhanazneen,
    Please check this forum thread : 
    There is one project for ZedBoard, and an entire discussion on how to make the pin-out. If you are still having issues, please tag me in here. Thank you. 
    Best Regards,
    Bogdan Vanca  
  24. Like
    BogdanVanca got a reaction from JColvin in zynq ps and conventional miccroprocessor   
    Hello @Arjun,
    A conventional microprocessor is an IC which has only the CPU inside, without RAM, ROM, or any others peripherals. If you check this link on page 5 :http://www.ioe.nchu.edu.tw/Pic/CourseItem/4468_20_Zynq_Architecture.pdf you will found out that, aside the dual arm cortex processor, the processing system of the Zynq architecture has a lots of other peripherals. 
    Best Regards,
    Bogdan Vanca
  25. Like
    BogdanVanca got a reaction from JColvin in Global variables in SDK   
    Hello @Antonio Fasano
    A global variable is a variable that is declared outside all functions and it can be used in all functions, but into the same c/cpp file. If you want to pass variables between two different files, you need functions. For example you declare the prototype of the function into the main.c file and the body into the echo.c file. In this way you can pass your "int x" variable trough one of the function parameters. I hope I was clearly enough.
     
    Best Regards,
    Bogdan Vanca