Hi @John J,
I'm sorry for my late response.
The generic project creation script will be very helpful. To make everything a little bit more clear, the system initialization trough psu_init() is returning back an DDR initialization error, and when you are enabling the debug prints by adding the FSBL_DEBUG_INFO symbol, this error is disappearing?
If this is the case, I have to somehow recreate your setup, because I'm not experiencing the same issue on my local machine. You also said that you are experiencing this in 2022.1, and you didn't had problems in 2020.1, am I right?
Best regards,
Bogdan Vanca
BogdanVanca got a reaction from John J in I can create a working bare metal project for a Genesys-ZU in Vitis 2022.1, but it has one issue...
