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BogdanVanca

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Posts posted by BogdanVanca

    PL to PS interrupts on Genesys ZU-3EG

    in Embedded Linux

    Posted

    Hello @Laerke,

    I've recreated the demo on Genesys ZU-3EG, and it works.

    The first mistake that I saw in your project was the value for the #define XPAR_FABRIC_EXT_IRQ_INTR. It is 121U not 89U. Please check  ug1085https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/System-Interrupts?tocId=PD9FTob69sVTjQEM8sOQ~g  chapter 13, table 13-1. 121-128 for pl_ps_irq0 and 136-143 for pl_ps_irq1.

    Code bellow:

    #include <stdio.h>
    #include "platform.h"
    #include "xil_printf.h"
    #include "xparameters.h"
    #include "xscugic.h"


    XScuGic InterruptController;
    static XScuGic_Config *GicConfig;

    void ExtIrq_Handler(void *InstancePtr)
    {
      xil_printf("ExtIrq_Handler\r\n");
    }

    int SetUpInterruptSystem(XScuGic *XScuGicInstancePtr)
    {
      Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler) XScuGic_InterruptHandler, XScuGicInstancePtr);
      Xil_ExceptionEnable();
      return XST_SUCCESS;
    }


    int interrupt_init()
    {
      int Status;

      GicConfig = XScuGic_LookupConfig(XPAR_SCUGIC_0_DEVICE_ID);
      if (NULL == GicConfig) {
        return XST_FAILURE;
      }

      Status = XScuGic_CfgInitialize(&InterruptController, GicConfig, GicConfig->CpuBaseAddress);
      if (Status != XST_SUCCESS) {
        return XST_FAILURE;
      }

      Status = SetUpInterruptSystem(&InterruptController);
      if (Status != XST_SUCCESS) {
        return XST_FAILURE;
      }

      Status = XScuGic_Connect(&InterruptController, XPAR_FABRIC_PL_PS_IRQ0_0_INTR, (Xil_ExceptionHandler)ExtIrq_Handler, (void *)NULL);
      if (Status != XST_SUCCESS) {
        return XST_FAILURE;
      }

      XScuGic_Enable(&InterruptController, XPAR_FABRIC_PL_PS_IRQ0_0_INTR);

      return XST_SUCCESS;
    }


    int main()
    {
        init_platform();
        interrupt_init();
        print("Hello World\n\r");
        print("Successfully ran Hello World application");
        cleanup_platform();
        return 0;
    }

     

    xdc

    set_property -dict { PACKAGE_PIN AB14  IOSTANDARD LVCMOS33 } [get_ports { pl_ps_irq0_0 }]; #sw[3]

     

    I will try to add the project to our GitHub repository.

    Best Regards,

    Bogdan Vanca

     

     

     

     

    I can create a working bare metal project for a Genesys-ZU in Vitis 2022.1, but it has one issue...

    in FPGA

    Posted

    Hi @John J,

    Thank you very much for the script. We are also providing a very similar approach with our vitis-scripts

    Can you please tell me what DDR4 module you are using?  I'm not been able to replicate your issue on my local machine. 

    I've published  the release for the Hello-World app for our 5EV variant in 2022.1 here

    Can you please move on to the 5ev/master branch and build the project with our scripts? (You can also use your script, but please make sure that you are using the right fsbl sources, check the attached zip)

    Steps are :

    git clone --recursive <URL>

    cd Genesys-ZU/

    git switch 5ev/master

    git submodule init

    git submodule update

    cd sw/

    git submodule init

    git submodule update

    Launch the Xilinx Vitis 2022.1 and open the XSCT Console.

    source [getws]/../src/checkout.tcl

    If you open this script you will see that is more or less similar to the one the you provide me, the only difference is that is building the FSBL app from scratch.   For now, I cannot pinpoint anything but I will continue my investigation and I will keep you updated.

    src.zip

    I can create a working bare metal project for a Genesys-ZU in Vitis 2022.1, but it has one issue...

    in FPGA

    Posted

    Hi @John J,

    I'm sorry for my late response.

    The generic project creation script will be very helpful.  To make everything a little bit more clear, the system initialization trough psu_init() is returning  back an DDR initialization error, and when you are enabling the debug prints by adding the FSBL_DEBUG_INFO symbol, this error is disappearing? 

    If this is the case, I have to somehow recreate your setup, because I'm not experiencing the same issue on my local machine. You also said that you are experiencing this in 2022.1, and you didn't had problems in 2020.1, am I right?

    Best regards,

    Bogdan Vanca

    Genesys ZU-5EV HDMI Demo Error

    in FPGA

    Posted

    Hi @vcb1,

    Bellow is the guide for importing the archive.

    1. First, launch Vitis.

    1_.thumb.PNG.ad87b96c993ff124b343c199faa66068.PNG

    2. Go to Import->Vitis project exported zip file-> Next-> Navigate to the project archive

    2_.thumb.png.72ebcd5989b9623757c769d26e81ee54.png

    3. Import archive.

    3_.thumb.png.8e2b3e755bf00df0cb99a0e14ca9c0c3.png

    4.  Your workspace should look as in picture bellow

    4_.thumb.png.e6db502ad98151c022871f6e4ce9fd21.png

    5. Go to 5ev_boot.sprj-> Change target platform for the current project..

    5_.thumb.png.b7a77a38be839c71d8c0874276556bee.png

    6. Simply click OK.

    6_.thumb.png.e8f08cf3ccc484d9dc835b56fe0da4fd.png

    7.  Click YES.

    7_.thumb.png.388a5f88fc4cb101a92d427133c6cb9d.png

    8. Repeat this for all the project and project systems that are existing into the workspace:

    5EV_boot:

     -> 5ev_fsbl.prj, 5ev_pmufw.prj, 5ev_boot.sprj

    5ev_hdmi_demo_system:

    -> 5ev_hdmi_demo.prj, 5ev_hdmi_demo_system.prj.

    This should clean up all the paths for the .xpfm files.

    9. Verify the paths for the lscript file to be  ../src/lscript.ld. This verification should be done for the 5ev_fsbl.prj, 5ev_pmufw.prj and 5ev_hdmi_demo.prj.

    15_.thumb.png.98cb6b88cc95291ca1d6b890ea8c010f.png14_.thumb.png.47448c9a4a90d21d226371a235f1e2ce.png13_.thumb.png.c1bca9ab953c95156dbc8cb7b2194a71.png

    10. Verify the paths for the bsplib/lib from each makefile.

    Also verify the XPFM_PATH, if something is wrong go back to step 5.

    17_.thumb.png.8152afafd82e2d83338a6cf00fcd02fc.png

    11. Verify the build configuration. If you are in Debug mode, but you are targeting a release configuration, your paths wont get updated. Go to Manage Configuration-> Verify the active configuration.

    20_.thumb.png.30cfdff0230d97300474fc1166f846f0.png19_.thumb.png.ec691665843d48d1d8a6185a46ea2b43.png

    And I think those are all. Quite a hustle for simply importing a project.

    I personally recommend the git approach. If you encounter any issues please let me know.

     

    Best Regards,

    Bogdan Vanca

    18_.png

    Genesys ZU-5EV HDMI Demo Error

    in FPGA

    Posted · Edited by BogdanVanca

    Hi @vcb1,

    This is the guide for cloning the project and building it from scratch.  First you will have to download the git bash for windows from here https://git-scm.com/.

    After that you go to the fallowing repo: https://github.com/Digilent/Genesys-ZU and copy the repository URL.

    GOtogihub_1.thumb.PNG.1507ead9710a432132a3916d959df10e.PNG

    Chose folder locally on your computer for cloning the repository and launch the fallowing  command.

    Step 1.  Clone the project repository and initialize all the submodules. 

    $ git clone git@github.com:Digilent/Genesys-ZU.git

    Go inside the repository

    $ cd Genesys-ZU/

    Checkout on the 5ev hdmi demo branch.

    $ git checkout 5ev/demo/hdmi

    Initialize and update all the submodules branches.

    $ git submodule init

    $ git submodule update

    Change directory to ./sw folder.

    $ cd sw/

    Initialize and update the embeddedsw submodule.

    $ git submodule init

    $ git submodule update

    The detailed procedure is shown bellow.

    GOtogihub_14.thumb.PNG.82a648ed7ed8cbc3f8658dedc7b19ea1.PNG

    Step 2.  Build the project.

    Launch Vitis with the workspace set to the repository's sw/ws folder.

    GOtogihub_6.thumb.PNG.f6fcce9e73582367e0cf7c82d547688d.PNG

    Open XSCT Console through the Xilinx > XSCT Console option in the menu bar at the top of the window.

    GOtogihub_7.thumb.png.125af9b24f56ef91f6640dbbad2d994a.png

    Make sure the current path is correctly set to  ../Genesys-ZU/sw/ws

    GOtogihub_10.thumb.PNG.0e93fecb68daf5b8f97253d1c7a6a833.PNG

    Build the project with the fallowing command:

    source [getws]/../src/checkout.tcl

    GOtogihub_11.thumb.PNG.fa8ed8508a5c2b085be6dce4ed76e09e.PNG

    Watch as your workspace gets populated and build.

    GOtogihub_12.thumb.PNG.1de7655c8a97096844d567eec925f4ac.PNG

    This will take some time....

    You can ignore the warnings that are printed on the console.

     

    GOtogihub_13.thumb.PNG.d0ff0b91b4174a95dbaf028c4a666c20.PNG

    When everything is done you simply have to give a path for the fsbl file, and deploy the project on your board. If you encounter any issues please let me know.

     

    When I'm done, I will come back with the second guide for importing the project from the release archive.

    Best Regards,

    Bogdan Vanca

    GOtogihub_7.png

    Genesys ZU-5EV HDMI Demo Error

    in FPGA

    Posted

    Hi @vcb1,

    Thank you four pointing out this issue. The HDMI demo project reference manual doesn't include our latest workarounds for all the issues created by Vitis when you are trying to import a project. I recommend you to use the guide for the "Hello World Project", https://digilent.com/reference/programmable-logic/genesys-zu/demos/hello-world, in which for example I describe in detail how to add relative paths for the linker script. Another issue is indeed related with the path for the *.xpfm file, which needs to be updated immediately after you launch the Vitis app. For that, you simply have to go to each *.sprj and single-click on "Change target platform". Ideally, this will clean up the old project paths. It is quite a struggle to remove all the absolute paths, and Xilinx doesn't really give any help in this direction.

    A more faster and easier approach would be to simply clone the project repository.

    You git clone locally, launch Vitis from within the ./ws folder and simply run into the XSCT Console the fallowing command: `source [getws]/../src/checkout.tcl` This will populate your workspace with all the necessary sources and build everything from scratch.  More info can be found into the .README file.

    Right now, I'm trying to replicate all your issues, and I've started an "how-to" guide for building and running the project. I will keep you updated. 

     

     

    Genesys ZU debugging error

    in FPGA

    Posted

    Hi @John J,

    Our latest preset is https://github.com/Digilent/vivado-boards/tree/master/new/board_files/genesys-zu-3eg/D.0 

    For now, we don't have any plans to bring in any updates. If you are facing any issues, please let me know.

    Best Regards,

    Bogdan Vanca

    Genesys ZU debugging error

    in FPGA

    Posted

    Hi @John J,

    Your problem may be caused by not using our custom fsbl file. Our "Hello World" project adds the following https://github.com/Digilent/embeddedsw/tree/6e9e2fa973f2c27d3f979f3c07afdbe616f694a4 repository into the ws. One solution would be to manually clone the embededsw repository, and add it into your Vitis workspace.

    Xilinx ->Software Repositories-> New-> browse to the repository 

     

    Note: You need to delete your existing FSBL before you start re-building a new one.

    Best Regards,

    Bogdan

    Genesys ZU debugging error

    in FPGA

    Posted

    Hello @Richm,

     

    We found out that there is a "bug" with the "PSU__DDRC__DDR4_ADDR_MAPPING" parameter from the board preset file, that went under our radar. This parameter needs to be disabled in order to  return to the static DDR configuration operation in psu_init.c and the FSBL.  For that,  you need to go to \Xilinx\Vivado\2021.1\data\xhub\boards\XilinxBoardStore\boards\Xilinx\genesys-zu-5ev\C.0 and replace the existent preset file with the one that is attached to this message.

    After that, open your Vivado project and run in your tcl console the fallowing command:

    report_property [get_ips design_1_zynq_ultra_ps_e_0_0] -regexp .*PSU__DDRC__DDR4_ADDR_MAPPING.*

    If the preset was correctly applied, you should see the fallowing message:

    INFO: [Vivado 12-5777] IP Instance 'design_1_zynq_ultra_ps_e_0_0' cannot be used in a module reference:
    Property                             Type    Read-only  Value
    CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING  string  false      0

    If not, open your Zynq Ultrascale+ MPSOC IP and go to Presets->Apply Configuration, and browse to the preset that I gave you.

    Run again the command, and verify if "CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING" is 0.

    Note: In your project "design_1_zynq_ultra_ps_e_0_0" is the name of the Zynq MPSoc IP. You can find the name of your Zynq MPSOC by running the fallowing command:

    get_ips

    and searching for the one that has the "zynq_ultra_ps_e_0_0" extension.

    If this doesn't solve your issue, please let me know.

    This change will be available in a future minor revision, but I thought  that there is no need to make you wait until we publish it.

     

    Best Regards,

    Bogdan Vanca

    preset.xml

    Using Genesys Zu with AXI DMA to send data from PL to DDR4 RAM

    in FPGA

    Posted

    Hi @QI109,

    I'm assuming that you are using the 3EG variant.  

    If you want to send data from PL into the DDR4, you simply have to connect your AXI-DMA to one of the HP ports of the ZynqUltrascale+ MPSoC and use an psu_init.tcl file or an fsb.elf file for taking out of reset the A53. For this, you will have to migrate from Vivado to Vitis, where you can use our 3eg_fsbl.elf from our 3EG Hello World Demo, by downloading the corresponding zip file https://github.com/Digilent/Genesys-ZU/releases/tag/3EG%2FHELLO-WORLD%2F2020.1-1.  Regarding the High Performance Ports, you can choose between the HP0, HP1, HP2 or HP2 ports as it is shown in the Zynq UltraScale+ Device Technical Reference Manual page 1105 https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf.

    Thank you,

    Bogdan Vanca

    Vivado HLS Board Files for the ZyboZ7-20

    in FPGA

    Posted · Edited by BogdanVanca

    Hello @rzsmi,

    If you want to add Zybo Z7 board definition to Vivado HLS , you have browse to your Vivado installation folder. For example, on Windows : C:\Xilinx\Vivado  2017.4\common\config and open the VivadoHls_boards.xml file in notepad++. After this please add the fallowing line and save it :

    <board name="Zybo" display_name="ZyboZ7-20" family="zynq" part="xc7z020clg400-1"  device="xc7z010" package="clg400" speedgrade="-1" vendor="digilentinc.com" />

    Best Regards,

    Bogdan Vanca 

    PMOD MTDS without using IP

    in Add-on Boards

    Posted

    Hello @ArnaldoM,

    It's not that simple as you thinks. It's not like you power up the pmod and write some values into some registers and your rectangle gets drawn on your display. First you can start by doing  some reverse engineering to see exactly how the display gets initialized. For this you probably need to start from this function : bool MYDISP::begin(), because this function creates the interface object and initializes the underlying MTDS library for access to the display device. Also it establish contact with the firmware running on the shield and initialize for operation. After you finish with this, you can create you own start up sequence, and you can start drawing your rectangle. For this you need to create a function that will send your data packets to the shield. As you may think, every data packet has it's own register value. For example if you want to draw an rectangle, your data packed needs to be equal with 0x38. Same logic with the back-light, but with different register value. For more info, you can check the Display Shield Communications Protocol Definitions file or ProtoDef.h from Arduino IDE. Please check the fallowing link : https://reference.digilentinc.com/reference/software/mtds/start.  

    For the hardware architecture, because you have the PMOD version of MTDS, it's more naturally to go with the pmod interface and not spi. For this you need to create your own IP core that creates the bridge between the pmod interface and Zinq AXI.

    Considering how big the mtds libraries are, the discussion it's probably a little bigger than this :). 

     

    Best Regards,

    Bogdan Vanca     

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