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Everything posted by BogdanVanca

  1. Hello @macellan, That's because you've already added one. I can see it under the XADC System monitor.
  2. @Fred_HY Here you go. You can find in the attachment a boot bin with the project. You only have to copy the BOOT.bin on an SD card and move the jumper on SD. If it's not working, you have hardware issues. Bellow is a link with the entire project. It has been tested and upgraded to 2019.1. BOOT.rar
  3. Hello @Fred_HY, No, I didn't forgot. The project is just building.
  4. Hello @Fred_HY, I will send you a boot.bin with the project. Do you have an SD card? If not, I will assist you on programming the flash memory.
  5. The first file is the hardware platform for the second file. The second file it is an sdk workspace that generates a color-bar on your HDMI monitor. It doesn't have the same content as the Zybo-Z7-20-pcam-5c.sdk file. At this point I'm only trying to see if it is something wrong with your monitor or the cable that you use for the monitor. If we can take that out from the equation, we can concentrate on the input side of the project. Did you modified anything on the project? Here I'm also referring to any repackaging of the existent IPs.
  6. Ok. This critical warnings are expected. At first we can at least try to see if your monitor has any problems. I will send you a project that tests this. You should see a color bar on your monitor. handoff_2.rar sdk.rar *If you have any problems, please let me know
  7. Ok, so at least you have some image on your monitor. 1. Do you have some critical warnings in Vivado? 2. Have you tried with a different FFC cable? 3.Is the FFC cable correctly connected?
  8. Hello @Fred_HY, So, you are saying that you are not able to run our pcam demo in Vivado 2018.2? More exactly this one:
  9. Hello @Fred_HY, Please open a different forum thread. I don't want to mix two different discussions in a single forum thread. Thank You.
  10. No. Just open the sdk workspace and test the application.
  11. I'm sending you the sdk workspace together with the handoff. Please open sdk workspace, and at the same time delete the existent metadata. It will be regenerated after you start your own Xilinx SDK. Please tell me if it works. You should see a color bar on your screen. sdk_workspace.rar @Laumont, if you have any problems, please let me know.
  12. Hello @Laumont, I've just finished the bitstream for a simple Test Pattern Generator to VDMA on Zybo z7 and the HDMI output. Right now I'm working on the software part, and after that I will send you the project. I don't have a Zybo, so you would need to test it for me.
  13. Hello @Laumont, Ok @Laumont, Sorry again for my late response. I promise to you that we will have a more consistent correspondence. What would you say to start from the existent project that we have on our github for Zybo Z7 and Pcam 5C. We can eliminate the parts that you don't need and add the parts that you are working on. For example we can simply eliminate the entire MIPI-DPHY -> MPICSI-RX->AXI Bayer->Video Scaler and keep the rest. This will solve the HDMI output problem. After that we can focus on how to read data from the SD card and transferring the data trou
  14. Hello @Laumont, I'm sorry for my late reaponse. Do you want to now how to drive the HDMI output on Zybo Z7, or how to read from the sd card and go on from there towards the HDMI output and monitor?
  15. Do you have PULLUP TRUE on both I2C lines in your xdc file?
  16. Hello @john_joe, I will take a shot in the dark, and I will ask you what it is your target clock used for synthesis in HLS? It has to have the same period with the pixel clock from your Vivado design.
  17. Hy @linasr, Can you please attach me the entire file that dose the I2C communication with the camera? I would like to have a look and see if I can spot anything wrong. Best Regards, Bogdan Vanca
  18. Hello @bitslip, Sorry for my late response. 1. What is the highest frame rate that will still work with the red part of the video chain ( given a 2560 W x 2 H resolution ) ? Regarding the block design, the limitation will come from the maximum total bit rate that the MIPI-CSI Receiver has for your device speed grade. For Zynq-700 this is equal with 1260 Mb/s. So you could simple calculate: Total bit rate = 2560(w) * 2(h) * maximum frame rate(fps) * Nr. of bits per pixel(bit/pixel) = 1260 Mbp/s. So, theoretically you could go as high as you want, as long as you are
  19. Yes, now everything is much clear for me. I will consult my colleagues tomorrow and I will try to give you a more detailed answer.
  20. Yes, it can be a little bit confusing. Only the VDMA, rgb2dvi etc... I was referring to this header file, because you have to make sure that you are providing the correct pixel clock for the resolution that you are expecting to see on you monitor. So, for a more simple overview of the entire block design, you can devide the entire project in two: before the frame buffer and after the frame buffer. There is a pixel clock for the incoming sensor data, although the things are a little bit more complicated with the MIPI interface, and a pixel clock used for displaying the data at a chosen re
  21. Right now, the Stream clock that enters into the Bayer IP is the same aclk used trough the entire design. The IP doesn't have any internal constraint file for it, so I cannot put my finger on a value. In the current project, I think that it is at 150 MHz for covering the 1920x1080 resolution. Ideally, the highest supported frequency for this IP is equal with the video_aclk of the MIPI-CSI RX. For Zybo, this would be 175 MHz. You can achieve a higher throughput by increasing the Pixels per clock option to Dual or Quad. I presume that is already done in the project.
  22. Hello @bitslip, The next thing would be to make sure that the video clock generator outputs the right pixel clock for you desired resolution. For that you would have to configure the video clock generator. In the Zybo Project, this is done in VideoOutput.h (line 104 to 112), were the 742.5 MHz clock gets divided by three different factors for each resolution. The pixel clock represents the total number of pixels that need to be sent every second, or Pixel clock = Htotal × Vtotal × frame rate. In order to have space for the maximum frame rate, you will have to go with the high
  23. Hello @bitslip, All the registers used for image windowing are between 0x3800 and 0x3814. You can find more info. by going to page 40 fro the fallowing datasheet: Best Regards, Bogdan Vanca
  24. Hello @[email protected], You can find more info in the fallowing datasheet: At 120 fps, you can only go with QVGA. The bigger the frame rate, the smaller the format would be. So, if you want to reach 120 fps, you will have to rewrite the 0x3800 ~ 0x3814 registers, for image windowing. You can find more info by going to page 40 and 41, from the same datasheet . For 90 fps you will have to go with the VGA format. The 12 fps cannot be obtain. *Also please make sure that you provide the co
  25. Hello @ddmdd1989, This error says that the ports are not connected in the XDC file. Best Regards, Bogdan Vanca