BogdanVanca

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  1. Hello @Alpha_HW, The OOB demo configures the UART1 interface as EMIO, thus the RX and TX pins are exposed to the PL side. You can connect them to any pins you want. Best Regards, Bogdan Vanca
  2. Hi @QI109, I'm assuming that you are using the 3EG variant. If you want to send data from PL into the DDR4, you simply have to connect your AXI-DMA to one of the HP ports of the ZynqUltrascale+ MPSoC and use an psu_init.tcl file or an fsb.elf file for taking out of reset the A53. For this, you will have to migrate from Vivado to Vitis, where you can use our 3eg_fsbl.elf from our 3EG Hello World Demo, by downloading the corresponding zip file https://github.com/Digilent/Genesys-ZU/releases/tag/3EG%2FHELLO-WORLD%2F2020.1-1. Regarding the High Performance Ports, you can choose betwee
  3. Hello @macellan, That's because you've already added one. I can see it under the XADC System monitor.
  4. @Fred_HY Here you go. You can find in the attachment a boot bin with the project. You only have to copy the BOOT.bin on an SD card and move the jumper on SD. If it's not working, you have hardware issues. Bellow is a link with the entire project. It has been tested and upgraded to 2019.1. https://www.dropbox.com/s/eyy5lq4tp48usg8/2019_1.rar?dl=0 BOOT.rar
  5. Hello @Fred_HY, No, I didn't forgot. The project is just building.
  6. Hello @Fred_HY, I will send you a boot.bin with the project. Do you have an SD card? If not, I will assist you on programming the flash memory.
  7. The first file is the hardware platform for the second file. The second file it is an sdk workspace that generates a color-bar on your HDMI monitor. It doesn't have the same content as the Zybo-Z7-20-pcam-5c.sdk file. At this point I'm only trying to see if it is something wrong with your monitor or the cable that you use for the monitor. If we can take that out from the equation, we can concentrate on the input side of the project. Did you modified anything on the project? Here I'm also referring to any repackaging of the existent IPs.
  8. Ok. This critical warnings are expected. At first we can at least try to see if your monitor has any problems. I will send you a project that tests this. You should see a color bar on your monitor. handoff_2.rar sdk.rar *If you have any problems, please let me know
  9. Ok, so at least you have some image on your monitor. 1. Do you have some critical warnings in Vivado? 2. Have you tried with a different FFC cable? 3.Is the FFC cable correctly connected?
  10. Hello @Fred_HY, So, you are saying that you are not able to run our pcam demo in Vivado 2018.2? More exactly this one: https://github.com/Digilent/Zybo-Z7-20-pcam-5c?
  11. Hello @Fred_HY, Please open a different forum thread. I don't want to mix two different discussions in a single forum thread. Thank You.
  12. No. Just open the sdk workspace and test the application.
  13. I'm sending you the sdk workspace together with the handoff. Please open sdk workspace, and at the same time delete the existent metadata. It will be regenerated after you start your own Xilinx SDK. Please tell me if it works. You should see a color bar on your screen. sdk_workspace.rar @Laumont, if you have any problems, please let me know.
  14. Hello @Laumont, I've just finished the bitstream for a simple Test Pattern Generator to VDMA on Zybo z7 and the HDMI output. Right now I'm working on the software part, and after that I will send you the project. I don't have a Zybo, so you would need to test it for me.
  15. Hello @Laumont, Ok @Laumont, Sorry again for my late response. I promise to you that we will have a more consistent correspondence. What would you say to start from the existent project that we have on our github for Zybo Z7 and Pcam 5C. We can eliminate the parts that you don't need and add the parts that you are working on. For example we can simply eliminate the entire MIPI-DPHY -> MPICSI-RX->AXI Bayer->Video Scaler and keep the rest. This will solve the HDMI output problem. After that we can focus on how to read data from the SD card and transferring the data trou