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BogdanVanca last won the day on May 3

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About BogdanVanca

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  1. BogdanVanca


    @Victor McKeighan I'm truly sorry for you. In this moment I'm suspecting an hardware issue. In order to be absolutely sure of that, please send me your Impact project, and also the bit file and MCS file. Thank you. Best Regards, Bogdan Vanca
  2. BogdanVanca


    @Victor McKeighan I'm attaching you a document that takes you trough all the steps necessary to program the Quad SPI on CMOD S6. It uses ISE Impact. I look forward to hearing from you. Best Regards, Bogdan Vanca iMPACT SPI FLASH.docx
  3. Hello @jfdo Fernando, Theoretically yes, it should work. But, I personally think that would be extremely difficult. First of all, you cannot control the exact moment on which OpenScope Mz, for example, starts to sample your data. Or I have no idea if you can control the exact moment on which your external buffer starts to feed OpenScope. So, you probably may loose samples or you you will have a lots of zeros. With other words, it would be extremely difficult for you to sync the external buffer with the OpenScope. Also, all the signal processing can be made on 8k or 16k buffers, and trying to glue all your diagrams together it's not a very good idea. It's not very professional.
  4. Hello @jfdo, To answer on your first question, yes you can. But, either if you are talking about AD1 or AD2, the default scope buffer size is 8kSamples/channel. The WaveForms Device Manager provides alternate FPGA configuration files, with different resource allocation. With no memory allocated to the Digital I/O and reduced memory assigned to the AWG, the scope buffer size can be chosen to be 16kSamples/channel. In telephony, the usable voice frequency band ranges from approximately 300 Hz to 3400 Hz. So your sample rate has to be around 8 kHz. That means, you can record 1s of audio data. Or 2s if you chose to have 16kSamples/channel. I can recommend to you the OpenScope MZ, please check this link : , and that is because, OpenScope MZ comes with a maximum buffer size of 32640 samples per channel, giving you another 2s of audio data. You can export your acquired data and save it as a .csv file. After that, you can import it back and do the signal processing. For your third and four question, yes you can. You only need to be sure that your mic output doesn't go higher than the maximum input voltages limits, wich are up to ±25V on each input (50V differential).
  5. BogdanVanca

    Configuration: XADC

    Hello @theAsker, To accommodate bipolar signals, your analog input must be configured to bipolar mode. Bipolar mode is selected by writing to configuration register 0 from control registers. From what I found, this would be the third register from the 40h to 42h configuration registers (check table 3-4 page.43 from the attached document). I never tried to reconfigure the xadc from SDK, but I'm quite sure that you are not looking into the right header file. Please check this one : xadcps_hw.h. This header file contains identifiers and basic driver functions (or macros) that can be used to access the XADC device through the DeviceConfig Interface of the Zynq. If you go to line 281, you will find this : #define XADCPS_CFR0_DU_MASK 0x0400 /**< Bipolar/Unipolar mode */. Try to work it from here and tell me if you obtain some results. I am looking forward to hearing from you. cheers, Bogdan Vanca ug480_7Series_XADC.pdf
  6. BogdanVanca

    NetFPGA Sume micro usb replacement

    Hello @jorge23, This is the Micro USB Connector that you are looking for : WMRU2AB-05FLB2DSR-4.0. I'm attaching you the mechanical document , in case is hard for you to find this specific part. Best Regards, Bogdan Vanca 163-451 WMRU2AB-05FLB2DSR-4(1.0mm) (2).pdf
  7. BogdanVanca

    Connect two Pmods to the same port

    Hello @Nachiket Karve, Have you tried to connect them manually in the xdc file?. Thank you, Bogdan
  8. BogdanVanca

    MIPI CSI-2 interface on Nexys-4 DDR board possible?

    Hello @koen.lostrie, From my experience I can tell you that this is not feasible at all. There are a lot of problems with this along with those that you are already facing. For example you need to add termination resistors for the D-PHY lanes. Also the XADC has input serial resistors that will negatively affect your signals, and you probably need to get rid of them. We have done some signal integrity tests, and I can tell you that for what are trying to do is impossible to have a working project for a clock frequency higher than 210 Mhz. I am not going to enter here into more details. I consider that, the best solution for you would be to buy a Zybo-Z7 and use the onboard mipi-connector. PS: You can have LVCMOS33 and LVDS_25 on the same bank if you are using LVDS as inputs with the DIFF term termination OFF.
  9. BogdanVanca

    HDMI In to VGA out on Zybo

    Hello @cgarry, If you check the ip documentation, you will found out this paragraph : "The parallel pixel clock (PixelClk) is recovered by the use of a BUFR buffer. Since BUFR is restricted to a single clock region and the video data output from the core is synchronous to PixelClk, any downstream logic consuming video data is also restricted to this clock region. The option to re-buffer PixelClk introduces a BUFG after the BUFR and re-registers video data into the BUFG-domain. This will allow downstream logic to be placed anywhere on the device." With other words this feature is more related with logic consuming, and normally should not introduce any kind of timing errors. For a better analyze, can you please attach a screen shot, or a document with the errors that you receive? thank you, Bogdan
  10. BogdanVanca

    Camera pmod for Arty A7

    Hello @moe, Unfortunately we don't have any pmods cameras. And that is because the pmod connector is not very suitable for video applications. If you want better performances, along with other resources, I can recommend you the Pcam 5C But for that you need a board with a mipi-connector. Unfortunately arty z7 doesn't have one. Regarding to your question, the AES-PMOD-TDM114-G camera should be compatible with Arty z7. But, making them work together is an entire different story. You can try a different one, please check this link You also have in there an example project. You can start with that architecture and adapt it for HDMI. Best Regards, Bogdan Vanca
  11. BogdanVanca

    rgb2dvi IP customization Part 2

    Hello @dgottesm, On a first look, that's all that you have to do. Regarding to your second question, those xdc-files sticks to your ip-core. There are locally with your ip and, if you want, you can modify them with the help of "edit ip packager" option. But that is not necessary, and in most cases it is not even recommended. You need to add your own xdc-file which will basically overwrite those, and will make, as you said all the pins assignments. To see the exact order in which your files are compiling please check the "compile order" tab, from the vivado menu. So, your 27 MHz clock needs to be set in your own xdc or, you can try to dynamically generate it with "axi_dynclk" module. I think that, the second option would be a better idea. There is another option in which you can use MIG 7 series (Memory Interface Generator). This core can generate up to 5 additional different clocks. But, you can consider this as an option only if you already/use or you are willing to use the memory generator in your block design. Best Regards, Bogdan Vanca
  12. BogdanVanca

    rgb2dvi IP customization Part 2

    Hello @dgottesm, If you look into rgb2dvi module you will found out, on line 36 this sintax: "kClkPrimitive : string := "PLL"; -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true". So, by default the clock primitive is instantieted as an PLL. For an 27 Mhz it is impossible to respect the minimum value for the PLL VCO frequency. Please check table 38 from the attached document. But, it is possible to do it if you instantiante the clk primitive as an MMCM. In this case the low boundery for the MMCM VCO frequency is 600.00 Mhz. For more details you can check the Table 37 from the same document. So, you need to chose the value "5" for the "kClkRange", because that will outputs you an 675 Mhz frequency for the VCO (20 x 25). And that value respects the MMCM constraints and also the project constraints. Also, don't forget to set the 27 Mhz into the xdc file. A strong recommendation for you is to do all the modification manually into the vhdl's modules. And after that, if everything looks ok and you want go further into the block-design, you can do the same stuff there with the help of the "edit in ip packager" option. Answers for your questions: 1) Thats the minimum value if you instantiate the kClkPrimitive as an PLL. 2) For this question, you can take as an answer the above text. I hope I was clearly enough. I look forward to hearing from you. Best Regards, Bogdan Vanca ds181_Artix_7_Data_Sheet.pdf
  13. BogdanVanca

    Nexys2 Cypress eeprom iic file request

    Hello @rsip, Please try the solution attached to this message. Best Regards, Bogdan Vanca DigilentFX2Repair.rar
  14. BogdanVanca

    Zybo z7-20 Zynq Presets

    Hello @mohammadhgh, You can find the presets-file and other useful stuff on Digilent GitHub into the vivado-boards section( Our presets-file for zyboz7-20 is attached to this message. Best Regards, Bogdan Vanca preset.xml
  15. BogdanVanca

    Block RAM- Controller vs Stand Alone

    Hello @dgottesm, If you select the BRAM controller all the parameters except the ‘memory type” are greyed out as they are generated from the master (you can find more information in here: If you chose the Stand Alone Mode, you get more access, and you are also capable to modify the available parameters. In your case if you want to modify the memory-width, yes, you should select the stand alone mode. Best Regards, Bogdan Vanca