BogdanVanca

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BogdanVanca last won the day on September 19

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  1. BogdanVanca

    Genesys2 demo project - not able to regenerate bit file

    Hello @Venkat, What version of Vivado do you use ? I'm asking this because tcl. scripts are extremely version specific. For example the script that creates the Out of the Box demo for Genesys2 will work only with Vivado 2015.4. Additionally, what edition of Vivado are you using? The free WebPACK edition will not be able to generate a bitstream for any Genesys 2 projects since it's chip is not supported in WebPACK. Best Regards, Bogdan Vanca
  2. Hello @bklopp, I don't have a lot of experience with scripts, but this is what Xilinx does for zcu102. See if it helps you . <interface mode="slave" name="user_si570_sysclk" type="xilinx.com:interface:diff_clock_rtl:1.0" of_component="user_si570_sysclk"> <parameters> <parameter name="frequency" value="300000000"/> </parameters> <preferred_ips> <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/> </preferred_ips> <port_maps> <port_map logical_port="CLK_P" physical_port="user_si570_sysclk_p" dir="in"> <pin_maps> <pin_map port_index="0" component_pin="user_si570_sysclk_p"/> </pin_maps> </port_map> <port_map logical_port="CLK_N" physical_port="user_si570_sysclk_n" dir="in"> <pin_maps> <pin_map port_index="0" component_pin="user_si570_sysclk_n"/> </pin_maps> </port_map> </port_maps> </interface> Best Regards, Bogdan Vanca
  3. BogdanVanca

    BASYS3 board - XADC ports

    Hello @donwazonesko, Please check this document : https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf for more info. "- what's the sampling rate (i think its 1 Mpsp)?" The sampling rate is indeed 1 MSPS. "- what's the delay between ports ?" Can you please be more specific ?. Are you referring to the delay between conversions ? If yes, 26 ADCCLK cycles are required to acquire an analog signal and perform a conversion. This implies a maximum ADCCLK frequency of 26 MHz. "- is it compatible with microphone output (diff or single ended)?" Probably yes. But you have to make sure that the microphone output doesn't exceeds 500 mV for bipolar mode and 1 V for unipolar mode . For more info, please check this document : https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf. Best Regards, Bogdan Vanca
  4. BogdanVanca

    Basys 3 XADC

    Hello @Rohit kumar jain, Yes it is possible. The on board xadc has 16 different aux analog inputs. Best Regards, Bogdan Vanca
  5. BogdanVanca

    Looking for the right board

    Hello @HelplessGuy, Zybo-Z7 will satisfy your needs. It has an Ethernet connector and also an On-chip analog-to-digital converter (XADC). When you say "160kHz" you probably refer to the sample frequency. The on board analog to digital converter has an sampling rate of 1MSPS and 16 different aux channels. You could also look on Arty Z7-10/20 version (https://store.digilentinc.com/arty-z7-apsoc-zynq-7000-development-board-for-makers-and-hobbyists/), or even ZedBoard(https://store.digilentinc.com/zedboard-zynq-7000-arm-fpga-soc-development-board/). Or if you want to work with an FPGA based board, you can go with Arty-A7(https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/) or Nexys4 (https://store.digilentinc.com/nexys-4-artix-7-fpga-trainer-board-limited-time-see-nexys4-ddr/). I also depends on how much money do you want to spend. Best Regards, Bogdan Vanca
  6. BogdanVanca

    JTAG-HS3 right angle adapter or ribbon cable?

    Hello @Jim Kurdzo, Please check in here : https://store.digilentinc.com/jtag-2x7-ribbon-cable/ Thank you. Best Regards, Bogdan Vanca
  7. BogdanVanca

    DRAM or ON-CHIP-MEMORY

    Hello @Ram, In SDK, there is an linker script file that specifies where different sections of an executable are placed in memory. Please check "lscript.ld". All of those sections are user-configurable. For all of our projects we use the "ps7_ddr_0" memory section. Best Regards, Bogdan Vanca
  8. BogdanVanca

    Simple Dual Port BRAM

    Hello @newkid_old, Please check the fallowing links: 1. https://www.youtube.com/watch?v=gfpE81yMBwQ&amp;t=218s 2. https://www.youtube.com/watch?v=SGvYkA87W20 The first link is a tutorial that teach you how to correctly instantiate an BRAM ip-core. And the second one shows you how to create a test-bench for it (a simple write and read operation). In my opinion it would be much easier for you, an much faster, to create your own BRAM ip-core. And that is because, an BRAM is nothing more than an array of arrays. In VHDL it will look something like this : ""type BRAM is array (0 to 2**AddrBits - 1) of std_logic_vector(RAM_Width-1 downto 0);" where AddrBits and RAM_Width are constants that defines the size of your BRAM. The process of reading and write are done "simultaneous" into an single process. Something like this : "ram_process: process (clk) begin if Rising_Edge(clk) then if (We = '1') then -- when you want to write into you BRAM. BRAM(Addr) <= data_in; -- you store the input data on a given address. end if; data_out <= BRAM(Addr); -- after writing, you output your data. end if; end process ram_process;" After you test your top module, you can make your own ip-core, and finally add it to your block design. Best Regards, Bogdan Vanca
  9. BogdanVanca

    My Exercise 1C(Zynq Book Tutorial) didn't work fine

    Hello @greedyhao, Please check if "Led channel" it's the same with the one that is actually connected to Led's. Also try on to run your project with "Launch on Hardware (System Debugger) ". On a first glimpse your code looks ok, so you may have some hardware issues. Also please check if "Gpio" uses the correct Base Address. Thank you. Best Regards, Bogdan Vanca
  10. BogdanVanca

    Default Power-up Value of Registers

    Hello @Foisal Ahmed, What registers ? Can you please be more specific ? Thank you. Best Regards, Bogdan Vanca
  11. BogdanVanca

    programming guide of zynq

    Hello @Ram, Please check this link : https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq-server/start "This guide will provide a step by step walk-through of creating a Zynq based hardware design using the Vivado IP Integrator that will build over the Getting Started with Zynqguide by making use of the on-board Ethernet port and GPIOs for the Zybo FPGA board.". You can start from here, and use the same hardware logic but different type of application for uart, spi etc. Best Regards, Bogdan Vanca
  12. BogdanVanca

    Pcam 5C Demo on Zybo Z7-10

    Hello @Chakma, Please go trough this five steps, and after that tell me if your problem still persists: 1. Unplug the Usb cable 2. Go to Task Manager and end task the hw_server.exe 3. Plug it again 4.Program FPGA 5. Run application Thank you. Best Regards, Bogdan Vanca
  13. BogdanVanca

    issue with xadc header auxiliary input

    Hello @farhanazneen, Please check this forum thread : There is one project for ZedBoard, and an entire discussion on how to make the pin-out. If you are still having issues, please tag me in here. Thank you. Best Regards, Bogdan Vanca
  14. BogdanVanca

    Global variables in SDK

    Hello @Antonio Fasano A global variable is a variable that is declared outside all functions and it can be used in all functions, but into the same c/cpp file. If you want to pass variables between two different files, you need functions. For example you declare the prototype of the function into the main.c file and the body into the echo.c file. In this way you can pass your "int x" variable trough one of the function parameters. I hope I was clearly enough. Best Regards, Bogdan Vanca
  15. BogdanVanca

    zynq ps and conventional miccroprocessor

    Hello @Arjun, A conventional microprocessor is an IC which has only the CPU inside, without RAM, ROM, or any others peripherals. If you check this link on page 5 :http://www.ioe.nchu.edu.tw/Pic/CourseItem/4468_20_Zynq_Architecture.pdf you will found out that, aside the dual arm cortex processor, the processing system of the Zynq architecture has a lots of other peripherals. Best Regards, Bogdan Vanca