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BogdanVanca last won the day on May 3

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About BogdanVanca

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  1. MIPI CSI-2 interface on Nexys-4 DDR board possible?

    Hello @koen.lostrie, From my experience I can tell you that this is not feasible at all. There are a lot of problems with this along with those that you are already facing. For example you need to add termination resistors for the D-PHY lanes. Also the XADC has input serial resistors that will negatively affect your signals, and you probably need to get rid of them. We have done some signal integrity tests, and I can tell you that for what are trying to do is impossible to have a working project for a clock frequency higher than 210 Mhz. I am not going to enter here into more details. I consider that, the best solution for you would be to buy a Zybo-Z7 and use the onboard mipi-connector. PS: You can have LVCMOS33 and LVDS_25 on the same bank if you are using LVDS as inputs with the DIFF term termination OFF.
  2. HDMI In to VGA out on Zybo

    Hello @cgarry, If you check the ip documentation, you will found out this paragraph : "The parallel pixel clock (PixelClk) is recovered by the use of a BUFR buffer. Since BUFR is restricted to a single clock region and the video data output from the core is synchronous to PixelClk, any downstream logic consuming video data is also restricted to this clock region. The option to re-buffer PixelClk introduces a BUFG after the BUFR and re-registers video data into the BUFG-domain. This will allow downstream logic to be placed anywhere on the device." With other words this feature is more related with logic consuming, and normally should not introduce any kind of timing errors. For a better analyze, can you please attach a screen shot, or a document with the errors that you receive? thank you, Bogdan
  3. Camera pmod for Arty A7

    Hello @moe, Unfortunately we don't have any pmods cameras. And that is because the pmod connector is not very suitable for video applications. If you want better performances, along with other resources, I can recommend you the Pcam 5C But for that you need a board with a mipi-connector. Unfortunately arty z7 doesn't have one. Regarding to your question, the AES-PMOD-TDM114-G camera should be compatible with Arty z7. But, making them work together is an entire different story. You can try a different one, please check this link You also have in there an example project. You can start with that architecture and adapt it for HDMI. Best Regards, Bogdan Vanca
  4. rgb2dvi IP customization Part 2

    Hello @dgottesm, On a first look, that's all that you have to do. Regarding to your second question, those xdc-files sticks to your ip-core. There are locally with your ip and, if you want, you can modify them with the help of "edit ip packager" option. But that is not necessary, and in most cases it is not even recommended. You need to add your own xdc-file which will basically overwrite those, and will make, as you said all the pins assignments. To see the exact order in which your files are compiling please check the "compile order" tab, from the vivado menu. So, your 27 MHz clock needs to be set in your own xdc or, you can try to dynamically generate it with "axi_dynclk" module. I think that, the second option would be a better idea. There is another option in which you can use MIG 7 series (Memory Interface Generator). This core can generate up to 5 additional different clocks. But, you can consider this as an option only if you already/use or you are willing to use the memory generator in your block design. Best Regards, Bogdan Vanca
  5. rgb2dvi IP customization Part 2

    Hello @dgottesm, If you look into rgb2dvi module you will found out, on line 36 this sintax: "kClkPrimitive : string := "PLL"; -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true". So, by default the clock primitive is instantieted as an PLL. For an 27 Mhz it is impossible to respect the minimum value for the PLL VCO frequency. Please check table 38 from the attached document. But, it is possible to do it if you instantiante the clk primitive as an MMCM. In this case the low boundery for the MMCM VCO frequency is 600.00 Mhz. For more details you can check the Table 37 from the same document. So, you need to chose the value "5" for the "kClkRange", because that will outputs you an 675 Mhz frequency for the VCO (20 x 25). And that value respects the MMCM constraints and also the project constraints. Also, don't forget to set the 27 Mhz into the xdc file. A strong recommendation for you is to do all the modification manually into the vhdl's modules. And after that, if everything looks ok and you want go further into the block-design, you can do the same stuff there with the help of the "edit in ip packager" option. Answers for your questions: 1) Thats the minimum value if you instantiate the kClkPrimitive as an PLL. 2) For this question, you can take as an answer the above text. I hope I was clearly enough. I look forward to hearing from you. Best Regards, Bogdan Vanca ds181_Artix_7_Data_Sheet.pdf
  6. Nexys2 Cypress eeprom iic file request

    Hello @rsip, Please try the solution attached to this message. Best Regards, Bogdan Vanca DigilentFX2Repair.rar
  7. Zybo z7-20 Zynq Presets

    Hello @mohammadhgh, You can find the presets-file and other useful stuff on Digilent GitHub into the vivado-boards section( Our presets-file for zyboz7-20 is attached to this message. Best Regards, Bogdan Vanca preset.xml
  8. Block RAM- Controller vs Stand Alone

    Hello @dgottesm, If you select the BRAM controller all the parameters except the ‘memory type” are greyed out as they are generated from the master (you can find more information in here: If you chose the Stand Alone Mode, you get more access, and you are also capable to modify the available parameters. In your case if you want to modify the memory-width, yes, you should select the stand alone mode. Best Regards, Bogdan Vanca
  9. functions of pmod acl

    Hello @Pujith Krishna, If you press "ctrl" and click on the function prototype into the same time (ex: ACL_SetMeasure(&acl, 0);), you will jump to the function body. There, before every function you can find a text that gives informations regarding the function itself. Same with the headers. Best Regards, Bogdan Vanca
  10. create delay in verilog in cmod a7

    Hello @anurag, Try map enable_delay to one led and ~enable_delay to another one. And also for a better understanding, I recommend to you to make a test-bench of your top level module. Best Regards, Bogdan Vanca
  11. create delay in verilog in cmod a7

    Hello @anurag, I will not writing you the entire code, because I am more an VHDL guy. But the idea and the algorithm is the same. A good idea is to use a clock based delay, in which for a chosen clock period you start to number clock cycles until you reach a value that satisfy your delay. So, the best way to create a delay is by using a counter, find out how many clock cycles you need to wait in order to obtain the required delay, this depends to your clock period. In this case, the code should look something like this: always @ (posedge clk) begin if (counter == value_to_reach) begin // where value_to_reach is as it says the value to reach in order to obtain the desired delay counter <= 0;// reset your counter enable_delay = ~enable_delay ;// this toggles every time your required delay is attained. end else begin counter <= counter +1;// keep incrementing end end To go further than that, a good practice is to split your logic in half. For example, if you want a 1s delay, you can use the above algorithm to create your base time. In this case units of seconds, and after that you only need to increment every time you reach the number of seconds that you want to delay. This give you the possibility to create even greater delays. And also splits your counter variable in smaller parts. Regarding the pins, if you look into the CMOD A7 constraints file you will find the clock pin declared as : ## Clock signal 12 MHz #set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_14 Sch=gclk #create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {sysclk}]; The constraint file creates the connection between the ports of your top level module and the FPGA’s pins. So, if you want to blink you led for a desired period of time, you only need to map the enable_delay signal to one led from the constraint file. I hope me answer give you some clarification, an I look forward to hearing from you. PS: Be sure to initialize value_to_reach and enable_delay to zero. Best Regards, Bogdan Vanca
  12. Spartan 3E don't turn on the LCD

    Hello @Juan José, Because it is not clear right now if your problem comes from that fact that your LCD is out or you don't have the right code-sources we want to specify that, the Spartan 3E it's a Xilinx board. So, all the materials and the technical support were provided by them. Unfortunately it seems that they no longer give these materials, and the only thing that you can find right now on their website is the board reference document. That's all. We contacted them, and we hope that they will pass to us all the support documents and projects, that once were provided, or at least they will reactive the support webpage for this board. Until then, we will try our best to respond to all your issues. Best Regards, Vanca Bogdan

    Hello @zygot @nicolasp5186, I attached the topic as part of my answer because, in that post are provided a lot of useful information regarding to this question. Yes A7 and Basys3 aren't the same boards, but if you are trying to change the IO voltage from 3.3v to 1.8v, you use the same procedure. You need to find the power supply pin for the bank, desolder it, route a new wire with the appropriate voltage on it to the pin, and solder that in place. It's possible on A7 because you can output the 1V8 directly from the board but, it's not an easy job and we don't recommend it. Best Regards, Vanca Bogdan

    Hello @nicolasp5186, There is a similar topic on this forum that can provide an answer for your question. If you have any others questions please feel free to ask. Best Regards, Vanca Bogdan
  15. Can Electronic Explorer board powered by USB alone?

    Hello @imc_user1, No is not possible. For instrumentation and measurements you need to have the 12V power supply on. Cheers, Vanca Bogdan