BogdanVanca

Technical Forum Moderator
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  1. Zybo z7-20 Zynq Presets

    Hello @mohammadhgh, You can find the presets-file and other useful stuff on Digilent GitHub into the vivado-boards section( https://github.com/Digilent/vivado-boards). Our presets-file for zyboz7-20 is attached to this message. Best Regards, Bogdan Vanca preset.xml
  2. Block RAM- Controller vs Stand Alone

    Hello @dgottesm, If you select the BRAM controller all the parameters except the ‘memory type” are greyed out as they are generated from the master (you can find more information in here: https://www.xilinx.com/support/documentation/ip_documentation/blk_mem_gen/v8_4/pg058-blk-mem-gen.pdf). If you chose the Stand Alone Mode, you get more access, and you are also capable to modify the available parameters. In your case if you want to modify the memory-width, yes, you should select the stand alone mode. Best Regards, Bogdan Vanca
  3. functions of pmod acl

    Hello @Pujith Krishna, If you press "ctrl" and click on the function prototype into the same time (ex: ACL_SetMeasure(&acl, 0);), you will jump to the function body. There, before every function you can find a text that gives informations regarding the function itself. Same with the headers. Best Regards, Bogdan Vanca
  4. create delay in verilog in cmod a7

    Hello @anurag, Try map enable_delay to one led and ~enable_delay to another one. And also for a better understanding, I recommend to you to make a test-bench of your top level module. Best Regards, Bogdan Vanca
  5. create delay in verilog in cmod a7

    Hello @anurag, I will not writing you the entire code, because I am more an VHDL guy. But the idea and the algorithm is the same. A good idea is to use a clock based delay, in which for a chosen clock period you start to number clock cycles until you reach a value that satisfy your delay. So, the best way to create a delay is by using a counter, find out how many clock cycles you need to wait in order to obtain the required delay, this depends to your clock period. In this case, the code should look something like this: always @ (posedge clk) begin if (counter == value_to_reach) begin // where value_to_reach is as it says the value to reach in order to obtain the desired delay counter <= 0;// reset your counter enable_delay = ~enable_delay ;// this toggles every time your required delay is attained. end else begin counter <= counter +1;// keep incrementing end end To go further than that, a good practice is to split your logic in half. For example, if you want a 1s delay, you can use the above algorithm to create your base time. In this case units of seconds, and after that you only need to increment every time you reach the number of seconds that you want to delay. This give you the possibility to create even greater delays. And also splits your counter variable in smaller parts. Regarding the pins, if you look into the CMOD A7 constraints file you will find the clock pin declared as : ## Clock signal 12 MHz #set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_14 Sch=gclk #create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {sysclk}]; The constraint file creates the connection between the ports of your top level module and the FPGA’s pins. So, if you want to blink you led for a desired period of time, you only need to map the enable_delay signal to one led from the constraint file. I hope me answer give you some clarification, an I look forward to hearing from you. PS: Be sure to initialize value_to_reach and enable_delay to zero. Best Regards, Bogdan Vanca
  6. Spartan 3E don't turn on the LCD

    Hello @Juan José, Because it is not clear right now if your problem comes from that fact that your LCD is out or you don't have the right code-sources we want to specify that, the Spartan 3E it's a Xilinx board. So, all the materials and the technical support were provided by them. Unfortunately it seems that they no longer give these materials, and the only thing that you can find right now on their website is the board reference document. That's all. We contacted them, and we hope that they will pass to us all the support documents and projects, that once were provided, or at least they will reactive the support webpage for this board. Until then, we will try our best to respond to all your issues. Best Regards, Vanca Bogdan
  7. CMOD A7 35T DIGITAL IO VOLTAGE

    Hello @zygot @nicolasp5186, I attached the topic as part of my answer because, in that post are provided a lot of useful information regarding to this question. Yes A7 and Basys3 aren't the same boards, but if you are trying to change the IO voltage from 3.3v to 1.8v, you use the same procedure. You need to find the power supply pin for the bank, desolder it, route a new wire with the appropriate voltage on it to the pin, and solder that in place. It's possible on A7 because you can output the 1V8 directly from the board but, it's not an easy job and we don't recommend it. Best Regards, Vanca Bogdan
  8. CMOD A7 35T DIGITAL IO VOLTAGE

    Hello @nicolasp5186, There is a similar topic on this forum that can provide an answer for your question. If you have any others questions please feel free to ask. Best Regards, Vanca Bogdan
  9. Can Electronic Explorer board powered by USB alone?

    Hello @imc_user1, No is not possible. For instrumentation and measurements you need to have the 12V power supply on. Cheers, Vanca Bogdan
  10. Zybo and PmodCAN

    Hello @mbo, I have created for you a project that take one of the examples that I spoken earlier, and I adapted it for the Zynq Architecture. I also connected the PmodCAN to the standard Pmod Connector JE. I hope this will help you. Cheers, Vanca Bogdan Pmod_CAN.rar
  11. Zybo and PmodCAN

    Hello @mbo, On a first look your Block Design looks good. Please make sure that you validate it and you don't have any errors. As a starting point for your design, if you fallow into the "vivado library master" folder this path : vivado-library-master -> ip -> Pmods ->PmodCAN_v1_0 -> drivers, you can find example projects. Also in the main folder there is a ReadMe file, that gives you instruction on how to use the Pmod IP core for Zynq projects.I have reached out to more experienced engineers to see if they have more input for this issues. Best Regards, Vanca Bogdan
  12. Where is J14?

    Aa ok I didn't see your message. Good for you. If you have any other questions please feel free to ask. Best Regards, Vanca Bogdan
  13. Where is J14?

    Hello @deppenkaiser I attach to you a project for Arty z7-20 that writes "Hello world" on serial port. You need to install putty in order to view to message. The baud rate used in this specific project is equal with 115200. Please tell me if it works for you. cheers, Vanca Bogdan uart_zyn_arty_z7.rar
  14. Where is J14?

    Hello, We are more than happy to answer your questions, but this is a public forum and you need to take care of your bad language. The page with the J14 (USB-UART-Bridge) is not lost. In the Arty Z7 datasheet there are pages left intentionally blank, that is because it is our decision what we want to publish. You work on Arty z7 board, if you open the Zinq ip-core, in the PS zone you will find listed in the I/O Peripherals, the UART1 and UART0. You can manually select both of them. More than that, Vivado comes in your help and after you select "Run Block Automation " and "Run Connection Automation " the UART0 will be automatically selected. Basically if you want to make a "Hello World" application, your Block Design only needs to contain the Zynq ip-core. That's all. If you still need more assistance please tell me and I will gladly respond to your questions. Cheers, Vanca Bogdan
  15. Unknown Resource

    Hello, This guide will help you obtain Vivado Board Files for the Nexys 4, Nexys 4 DDR, Basys 3, Arty, Nexys Video, Zedboard and Zybo FPGA Boards. https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1 Also I attach to you the link to the repository that contains the board files used by Vivado. https://github.com/Digilent/vivado-boards cheers, Vanca Bogdan