Hello,
i run a block design with the rgb2dvi IP block on a nexys video board. The pixel clock is 146MHz and the output at the HDMI device is 912x1140@120Hz. The output feeds a DLP4500 prjector from TI. The prjector needs the resolution of 912x1140 pix. When I synthesis the project I always get a error message
[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets hdmi_i/clk_wiz_0/inst/clk_in1_hdmi_clk_wiz_0_1] >
hdmi_i/clk_wiz_0/inst/clkin1_ibufg (IBUF.O) is locked to IOB_X1Y124
hdmi_i/clk_wiz_0/inst/mmcm_adv_inst (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y3
The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.
Clock Rule: rule_mmcm_bufg
Status: PASS
Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
hdmi_i/clk_wiz_0/inst/mmcm_adv_inst (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X1Y3
and hdmi_i/clk_wiz_0/inst/clkf_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31
I use MMCM in the clocking wizard because PLL doesn't work with 146.0 MHz
Something went wrong with the PixelClk, here is the timing report.
How can I solve this problem...??
The project is under https://github.com/Johann-Schmid/hdmiAxi/
Have a great day & Thx