sgandhi

Members
  • Content Count

    50
  • Joined

  • Last visited

About sgandhi

  • Rank
    Frequent Visitor

Profile Information

  • Gender
    Female

Recent Profile Visitors

1243 profile views
  1. Hello, I am using the ZCU102 Ultrascale+ board and have replaced the default DDR memory with 32 GB - DDR4 (row address bits: 17, dual rank, column bits: 10, Bank group: 2 bits, Bank Address: 2 bits). In order to access the 32 GB of memory, 36 logical address bits will be used and I am not sure how they will be mapped to the DRAM addressing! Based on one thread in Xilinx forums, https://forums.xilinx.com/t5/Memory-Interfaces-and-NoC/How-to-map-the-AXI4-address-to-the-ddr4-memory-address/td-p/954407, for the requirement of BANK-ROW-COLUMN addressing, the AXI bytes could be mapped to the DRAM bits as Rank[34]_BankGroup[33:32]_Banks[31:30]_Row[29:13]_Column[12:3]_byteIndex[2:0]. But I am not sure if this is correct. UG 1087: Pg - 439:440 says that the ADDRMAP [0-11] registers acts as an intermediate mapper for HIF to DRAM addressing. Using the value of these registers in psu_init.c file, I am able to link the HIF address bits to DRAM addressing. On these pages, equation 17-1 returns HIF address bit number and the same expression returns AXI address bit number in equation 17-3 which seems conflicting! I am not sure how to connect the AXI logical and HIF addresses. In the case of logical addresses, the last three bits as a byte index and are always masked with 0's as mentioned in the above link on Xilinx forums. On the other hand, https://www.xilinx.com/support/answers/71359.html says that the HIF[0] is the DRAM column bit 0. It also says that: To perform the mapping from the byte-addressable AXI to DRAM addressing, add three bits to the HIF ADDRMAP representation described above for 64-bit DQ. From this line, I think that shifting the HIF address left by 3 bits may help to relate it with the AXI byte address of 36 bits! But everything seems confusing to me at this moment. My end goal is to decode the logical address say, 0x 8 BE00 7620 into DRAM addressing to identify which bits will be mapped to Row/Column/Bank/Bank Group/ Rank and so on.
  2. Thank you for the reply. I have posted the question on to Xilinx forums, hope to get the reply soon.
  3. Yes, the PL is working on the hardware acceleration of the design. Thank you for the reply.
  4. Hello, I am working with some really huge files that contains short reads (text) in millions of numbers. I am doing some processing on it in FPGA. I have a block design that has Zynq Ultrascale+ processor and few custom created IPs from HLS. The hardware is exported in SDK and then I am working on further to develop and application (bare-metal). At this point the short read file is in SD card which is read into the DDR memory. I have tested my application and that works. However, I wish to store this file in my computer and then transfer the data from the short read text file in blocks (say 10/20) via Ethernet which is then processed by the hardware in FPGA and the results are send back to the laptop/PC and then they are displayed. Once this block is done, next 10/20 lines of data is transferred from the short read file and same way the results are computed in FPGA. I have already worked with the lwIP echo server and web server application from Xilinx but I am not sure how to proceed ahead with what I wish to do. I have searched for many tutorials or any documentation but couldn't find any nice stuff to get the idea. I do have an idea that a client needs to be created on my PC and there must be a server on the FPGA but how exactly the flow should go? How exactly do I use the Ethernet options in block design as well as in SDK programming? How am I suppose to work on the PC for client side application? Do I need to consider the TCP Perf server template or lwIP echo server template in SDK while creating the bare metal application? Any help is highly appreciated in this regard. Thanks,
  5. Hello, I am working on string matching algorithms where I created an IP in HLS and then it is exported in Vivado to create a block design. I am using Zynq Ultrascale+ processor. I am using HP ports to connect the IP so that the interfaces can access the DDR memory. The block design right now has Zynq Ultrascale+ PS, HLS created IP (m_axi interfaces for ddr access, clk and reset interfaces), and AXI_Smartconnect. Since there are 4 High performance ports, I can have 4 copies of IP to reduce the execution time. However, I am just wondering what if I have to connect the 4 copies of IP using only one HP port because the other 3 HP ports are used some where else. I see that the execution times reduces but by a very small amount. Also, if I connect all the 4 copies of the same IP to only one HP port than how do I ensure that when coding in SDK, all 4 copies of IP start processing at the same time? Is there any specific way to do this in programming or any thing that takes care of this? I am using C programming and the driver functions of the IP that will be exported to the SDK in the design hardware platform folder. Also, I am working on a bare-metal application right now. Any tutorial or any help is highly appreciated. ---------------------------------------- Thanks,
  6. Hello, I would like to share the steps for working with two or more ARM Cortex processors on FPGA from SDK at the same time. I have been using CORE 0 and CORE 1 from the four 64-bit ARM cores available. The FPGA board that I am using is : Zynq UltraScale+ ZCU102-ES2 Evaluation Board (xczu9eg-ffvb1156-2-i-es2) from Xilinx. We start with the block design creation in Vivado Design Suite. This does not include any custom generated HLS IP. The block design contains the Zynq Ultrascale+ PS IP available in the Vivado IP catalog. The following steps can help you in making this project work : 1. Apply the "Reset Block Automation", once the IP is available in the block design window. Double click on it to change the configurations. I am using the 32 GB of DDR4 memory so the DDR configuration have been set accordingly. You can refer the ddr_config.png and ddr_config1.png images attached. 2. Remaining configurations remain the same. Connect the pl_clk0 port to maxihpm0_fpd_aclk on the Zynq PS IP. 3. Create the HDL Wrapper, Run the Synthesis, Implementation and Generate the Bit stream. 4. Export the Hardware into SDK and then create the two application projects as follows. Create the first application project for hello world. Name it say "core_0_hw". Please select the Processor as psu_cortex53_0 in the dialog box. Select the hello world template and create the application project. Under the source folder, helloworld.c can be modified to have any print statement or a series of statements. 5. Create the second application project say "core_1_hw" and select the processor as psu_cortex53_1 in the dialog box. Select the hello world template and create the application project.You can keep a different print statement here w.r.t to first application project to recognize the difference in the SDK terminal when running the project. SOMETHING IMPORTANT : The linker script decides where to place the program code in the memory, here it is DDR. Under the source tab, double click on the file "lscript.ld". The file will open in editor window. It should look something like the one in linkerscript.png file attached. The code is placed in the psu_ddr_0_MEM_0. Since both the cores share the same DDR, it is not possible to load both the project codes at same starting address. We need to change these addresses in the linker script of both the projects. The DDR4 range available in this case is : 0x00000000 - 0x7FFFFFFF. So, I allocated the range 0x00000000 - 0x3FFFFFFF to the linker script for first application project and 0X40000000 - 0X7FFFFFFF to the linker script for second application project. The changes to Base Addresses can be made directly by double clicking on the value and overwriting the new address value. You can save it using Ctrl+S. 6. Once both the projects are ready, under the "Run" tab, select Run configurations. Select the Xilinx System Debugger to run these projects. If you have exported the bit stream with the hardware platform, you will be able to program the FPGA from SDK itself. Check the boxes as shown in the image file run_config.png. Then under the application tab, select the parameters as shown in the image file app_tab.png. Once this is done, click the Run tab. 7. Make sure that FPGA board is ON and the COM port is connect properly. (Baud rate : 115200) 8. You can also open the XSCT console to monitor the status of the core. It may show like this when the applications are running on both core. Info: Cortex-A53 #0 (target 9) Running Info: Cortex-A53 #1 (target 10) Running 9. The SDK terminal should display the messages now. Hope this helps. Shyama Gandhi,
  7. Hello, I am working with HLS, Vivado and SDK environment. First of all, I have created an IP in HLS that is used in the block design of Vivado. The entire hardware platform design when exported to SDK allows us to work on the processor part! I have my design running but in it I am using the driver functions of HLS IP for passing some data structures and then collecting the results back to be displayed on SDK serial terminal. Is there any function or provision that helps me to find out the time taken by the HLS IP to perform the computations? Like the people who work with driver functions of HLS IP knows that it is pretty much simple to just use the functions in the header file to pass on the input arguments. Then Start the HLS core and wait till it is done! Once it is finished, we can read the results stored in the DDR memory. But is there anything or some time function or whatever that can be written in the SDK C code to know the CPU's or IP's execution time? Thanks. Shyama,
  8. Hello, I am working on lwip webserver in vivado 2018.1. The code for the webserver is in C language. I want to create a dynamic webpage that displays the value of the 32-bit system register according to my application. I came across the lwip documentation that uses an example for the web server. However, it is in 2014.3 and that creates a problem when I use it in 2018.1! Also, there is memfs folder in it that contains the .js, .css files and all! The example creates some image.mfs in ddr memory location! In my case, I have created a const char [ ] that has html code inside and I pass it in tcp_write( ) and the web page gets displayed! It works. I have also created javascript code in the html code itself that dynamically changes the content on the webpage through button onclick event. However, I want this to be change using the C variable in my code. So, how do I link the C global variable or local variable to the javascript? In simpler way, I tried to declare a global variable say UINT a=10. Then, on button onclick event, when javascript is executed, I tried to change the content on webpage using the variable "a". But it doesn't work! Does anyone knows how to make my C code and javascript code work together? For reference, I am attaching the html and javascript code below: const char testdata[]= "<html> <body> <button onclick=\"start()\"> Start the countdown </button> <p id=\"demo\"> This the main page for the test application of the web server...</p> <p id=\"ch1\"> Change me with variable a...</p> <div id=\"bip\"> </div> <script> var counter = 10; var intervalId = null; function finish() { clearInterval(intervalId); document.getElementById(\"bip\").innerHTML = \"THE END!\"; if(counter == 0) { var xhttp = new XMLHttpRequest(); xhttp.onreadystatechange = function(){ if(this.readyState == 4 && this.status == 200){ document.getElementById(\"demo\").innerHTML = this.responseText; }} } xhttp.open(\"GET\", \"ajaxinfo.txt\", true); xhttp.send(); } function bip() { if(counter == 0) finish(); else { document.getElementById(\"bip\").innerHTML = counter + \" seconds remaining\"; } counter--; } function start() { intervalId = setInterval(bip, 1000);} </script> </body> </html>"; I want to replace any <p> element with a global variable that will be declared in the C code that has this html code inside a const char array as shown above. Any help is highly appreciated. Thanks,
  9. Hello, I have been working on the lwIP web server and the index.htm file used as a web page for this application is creating a problem for me. There is image.mfs file which I download at the DDR address of 0x10000000. I verified in xparameters.h that the DDR is from 0x00100000 to 0x3FFFFFFF. When I download the image.mfs, it is done successfully and I get this at xsct console : dow -data image.mfs 0x10000000 0% 0MB 0.0MB/s ??:?? ETA 16% 0MB 0.3MB/s ??:?? ETA 34% 0MB 0.3MB/s ??:?? ETA 52% 0MB 0.3MB/s ??:?? ETA 70% 0MB 0.3MB/s ??:?? ETA 88% 0MB 0.3MB/s ??:?? ETA 100% 1MB 0.3MB/s 00:03 There after when I run the web server application I get this error: ********************************************************* -----lwIP Raw Mode Demo Application ------ link speed for phy address 1: 1000 ERROR: DHCP request timed out Configuring default IP 192.168.1.10 Board IP: 192.168.1.10 Netmask : 255.255.255.0 Gateway : 192.168.1.1 http server is running on port 80 Please point your web browser to http://192.168.1.10 platform_init_fs 4: ERROR: unable to locate index.html in FS *********************************************************** Error value of 4 means FR_NO_FILE for f_open function.... The code that is being used for platform_init_fs( ) is attached below. Also, in the example of lwIP, the memfs folder that contains the image,css, index.html and all.. is to be stored inside the project folder, and not specifically inside the .sdk folder?? I mean, is it sufficient for the files to be there in the main project folder, no matter wherever in the sub-directories? Any help is highly appreciated, platform_init_fs.txt
  10. sgandhi

    Webserver using Zybo Z7

    Hi @jpeyron, I tried to follow the steps from the blog you mention above but when it does not allow me the mount command saying permission denied.... However, I have tried working with FAT FS for sd card however, the lwIP webserver README.txt says that "The application expects web pages to be stored in RAM based FAT FS". So, is it the talking about storing the webpages in the computer's RAM? However, I am not able to figure out how do I do that? Incase of Xilinx forum, it takes much time to get back the reply!!! So, I am posting my question if there is anything you could help!
  11. sgandhi

    Webserver using Zybo Z7

    Hello @jpeyron, I was looking into some examples in the \lwip202....\examples and found one lwip webserver example that uses index.htm file present in FS! Now when I follow the readme.txt file for directions to execute the example, I see some steps as follows: ********************************************************************** Creating FAT image on Linux --------------------------- This requires root (sudo) access on the Linux host Following commands can be used on terminal to create FAT image to be used with webserver application: # create image file of 3MB dd if=/dev/zero of=example.img bs=512 count=6144 # format image with FAT /sbin/mkfs.vfat example.img # mount it mkdir /tmp/fs sudo mount -t vfat -o loop,rw example.img /tmp/fs/ # copy your webpages sudo cp -r webpages_dir/* /tmp/fs/ sudo umount /tmp/fs *************************************************************** And then it tells to run the application... I just tried to run the application w/o creating FAT image, which is obvious to give me the errors!! In order for the webserver to gain access to index.htm, the file needs to be present at the specific location. Is that why we create a FAT image on linux??? Also, the steps in readme.txt tells me to runs those commands on the terminal... How do I start with this? Is it talking about the sdk terminal? As per the directions, I added all the necessary source files and I also included the BSP settings as mentioned! Next step is to create a FAT image on linux... I am wondering how do I start with this! Thanks, Shyama.
  12. sgandhi

    Webserver using Zybo Z7

    Hi @jpeyron, So, do I just change echo.c using the file you provided? I am even suppose to change main.c when using the template of lwIP echo server in the SDK? Thanks for the reply, Shyama.
  13. sgandhi

    Webserver using Zybo Z7

    Hello, I have been successful in running the lwIP echo server on the Zybo Z7 board. However, I want to develop a web server on Zynq. I have gone through the lwIP documentation. However, in the discussion of this topic, I was successful in reading the .bin file from the SD card. Now I want to set up a web server on Zynq so I can command the server to read the .bin file from SD card and store it in the DDR. How do I start working on the web server. I have been searching a lot for the tutorial or anything that could make me understand in a simpler way but I failed to find any.! I also tried understanding the echo server C code in sdk however, after a point it seems too confusing to me. I could even think of modifying the echo server C code to develop a web server with some help, may be. The documentation of lwIP is confusing to me at this point.... Thanks, Shyama.
  14. sgandhi

    FAT32 with Zybo Z7

    Hello @jpeyron, Don't you think for just an arbitrary data type for a 2D array in SDK, it would be a hectic task to start from HLS? It seems to me that there has to be some way to deal with it in SDK.
  15. sgandhi

    FAT32 with Zybo Z7

    Hello @[email protected], @jpeyron, It worked. I got a .bin file from the MATLAB and then used Xilinx SDK to read a .bin file using 32 bit unsigned format. I am having a 2D array with 1 million rows and 4 columns. With each element represented as 32-bit unsigned number, the total size becomes ~15 MB. However, the maximum value in the array is 313,193 which can be represented with 19 bits only. However, I wish to work with multiple of 8-bits i.e., using 20 bits to represent each elements will give me 20 x 4 = 80 bits for each row instead of 19 x 4 = 76 (which is not a multiple of 8!). When I tried to generate a .bin file with each element of the array represented as 20 bits in MATLAB, the file is created successfully. For one million rows and each row of 80 bits, the total file size turns out to be 10,000,020 bytes (~9.53 MB). However, now having this file in the SD flash card, I want to change my code so that I have a 2D array declared as uint20, something like this! Now, this comes in the class of arbitrary precision data types and not the standard data types! My question is does SDK support arbitrary data types? If yes, which header file contains the definition? and how do I use them? (I am aware that HLS supports the arbitrary data types but not aware about the SDK). Thanks, Shyama.