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About fpga_123

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  1. Hi, You may want to have a look at the UART examples provided in C:\Xilinx\SDK\2019.1\data\embeddedsw\XilinxProcessorIPLib\drivers\scugic_v3_10\examples. Xilinx provides examples to work with polled mode, local echo mode and the interrupt mode. Bests,
  2. Not a good idea in this case then! Do you have any other suggestions on how I can work with changing the priority mask threshold for GIC? Many thanks,
  3. Can you please elaborate about what you mean by changing it in the IP library files itself? How can I do that? Thanks,
  4. Hello, Currently, I am working with the uart_interrupt example for PS UART 1 using freertos running on core0 for Zybo z7-10. The example template works fine but I wish to change the priority mask threshold of the scugic. I am also not sure if I am doing this right! With some work, I found that the Interrupt Priority Mask Register (ICCPMR) is used to set a priority mask threshold and in Zynq ARM-A9 this register is located at 0xF8F0 0104. Tracing down the code files associated with BSP, I found that during CPU Initialize a value of 0xF0 is written into this register. (8-bit priori
  5. Hello, I have a block design to drive the SSD using the AXI GPIO IP as illustrated in the figure. The SSD external interface is 8 bits(7 data bits + 1 select_segment bit). In SDK, I can write a C code to display the number from 0x0 to 0xF on one segment, however, I am not sure how to display number on both the segments at the same time from the SDK. I do have an idea that for using both the digits, we need to alternate between the two digits faster than our eye can perceive, say in terms of milli seconds. But how to achieve that in SDK? Also, is it possible to work on the logic of
  6. @DerekM That helps a lot. Thank you!
  7. Hello, Can anyone explain me the exact difference between Launch on Hardware (System Debugger) and Launch on Hardware (GDB) in Xilinx SDK?
  8. Hello, I am using the ZCU102 Ultrascale+ board and have replaced the default DDR memory with 32 GB - DDR4 (row address bits: 17, dual rank, column bits: 10, Bank group: 2 bits, Bank Address: 2 bits). In order to access the 32 GB of memory, 36 logical address bits will be used and I am not sure how they will be mapped to the DRAM addressing! Based on one thread in Xilinx forums, https://forums.xilinx.com/t5/Memory-Interfaces-and-NoC/How-to-map-the-AXI4-address-to-the-ddr4-memory-address/td-p/954407, for the requirement of BANK-ROW-COLUMN addressing, the AXI bytes could be mapped to t
  9. Thank you for the reply. I have posted the question on to Xilinx forums, hope to get the reply soon.
  10. Yes, the PL is working on the hardware acceleration of the design. Thank you for the reply.
  11. Hello, I am working with some really huge files that contains short reads (text) in millions of numbers. I am doing some processing on it in FPGA. I have a block design that has Zynq Ultrascale+ processor and few custom created IPs from HLS. The hardware is exported in SDK and then I am working on further to develop and application (bare-metal). At this point the short read file is in SD card which is read into the DDR memory. I have tested my application and that works. However, I wish to store this file in my computer and then transfer the data from the short read text file in blocks (s
  12. Hello, I am working on string matching algorithms where I created an IP in HLS and then it is exported in Vivado to create a block design. I am using Zynq Ultrascale+ processor. I am using HP ports to connect the IP so that the interfaces can access the DDR memory. The block design right now has Zynq Ultrascale+ PS, HLS created IP (m_axi interfaces for ddr access, clk and reset interfaces), and AXI_Smartconnect. Since there are 4 High performance ports, I can have 4 copies of IP to reduce the execution time. However, I am just wondering what if I have to connect the 4 copies of IP using
  13. Hello, I would like to share the steps for working with two or more ARM Cortex processors on FPGA from SDK at the same time. I have been using CORE 0 and CORE 1 from the four 64-bit ARM cores available. The FPGA board that I am using is : Zynq UltraScale+ ZCU102-ES2 Evaluation Board (xczu9eg-ffvb1156-2-i-es2) from Xilinx. We start with the block design creation in Vivado Design Suite. This does not include any custom generated HLS IP. The block design contains the Zynq Ultrascale+ PS IP available in the Vivado IP catalog. The following steps can help you in making this project work :
  14. Hello, I am working with HLS, Vivado and SDK environment. First of all, I have created an IP in HLS that is used in the block design of Vivado. The entire hardware platform design when exported to SDK allows us to work on the processor part! I have my design running but in it I am using the driver functions of HLS IP for passing some data structures and then collecting the results back to be displayed on SDK serial terminal. Is there any function or provision that helps me to find out the time taken by the HLS IP to perform the computations? Like the people who work with driver funct
  15. Hello, I am working on lwip webserver in vivado 2018.1. The code for the webserver is in C language. I want to create a dynamic webpage that displays the value of the 32-bit system register according to my application. I came across the lwip documentation that uses an example for the web server. However, it is in 2014.3 and that creates a problem when I use it in 2018.1! Also, there is memfs folder in it that contains the .js, .css files and all! The example creates some image.mfs in ddr memory location! In my case, I have created a const char [ ] that has html code inside and I pas