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  1. @jpeyron After looking further into this, I had finally figured out what the issue was but forgot to post what I had found on here. I managed to get the ILA working, and had observed the AXI interaction between the DMA and some of the other IP in my project. What I had found was that the DMA had not be 'setup' with enough time before actual data had been streaming. The AXI DMA Product guide explains it better by this quote: This explains why the first 4 ADC samples I had seemed off, and after those samples the data was good. In the end, I've learned yet again that most questions
  2. Hello All, I seem to be having an issue that I cannot quite track down the cause of... My overall goal is that I would like to write ADC samples into DDR memory via a DMA. I am able to DMA samples into the DDR successfully, except that the first couple values in DDR are incorrect. I've noticed that if I aquire some samples, and read the DDR, the first 4 are old samples which seem to update the next time I do an acquisition of ADC samples. I've also noticed that after the first DMA transfer, if I read the s2mm_length register, it seems to be a few transfers short of what I programmed the
  3. @[email protected] , I appreciate all of the help. I've changed from pins[0] to *pins, and declared two registers and initialized them to 0 and 1, but it doesn't seem to have had any affect on the speed. Maybe it is the I/O speed as you suggested. Also, the microblaze is currently configured for "performance" mode, which enables the 5 stage pipeline. I've attached the new assembly code, and it looks like it's still the same number of instructions. Best Regards, nystflame newAsmCode.txt
  4. Thank you both for your responses, i'll try my best to answer them individually: @jpeyron : Attached is a image of my block diagram. @[email protected] : Please see attached for assembly code. 1. I configured the microblaze with 32KB of instruction cache and data cache, and my program is running from the block memory onboard. 2. I hadn't turned on optimizations, but I believe I have that "-O3" option enabled now in the makefile. It increased the speed from 1.333MHz to 1.538MHz. 3. I've made them constants and the speed is still the same. 4. Setting the pin to 1
  5. Hello, Without implementing a timer, I had thought that toggling a GPIO pin and observing the result via a logic analyzer(has 100Megasample/sec). The Microblaze input clock is coming from the "ui_clk" from the MIG, which seems to be 83 MHz, but when observing the pin toggle the frequency is ~37 kHz. My method for toggling the pin is just an infinite while loop with two Xil_Out32 commands, one for turning the pin on, and the other command turns it off. Any debugging methods I should try as to why the frequency of this switching is so low? p.s. I've since moved from toggling via
  6. @jpeyron Thank you very much for all of his help! It's working great now for me after following what you had done. The voltage readings were off on the A0-A5 inputs because the function in the code you provided for calculating the raw to voltage is using 1.0V instead of 3.3V as the circuit suggests in the schematic you provided above.
  7. Hello, I am using the microblaze system with the xadc on an Arty board. I'm able to successfully read the internal voltages and temperatures of the chip, and I made some external pins (such as the VP/VN and Vauxp0 and Vauxn0). The pins which are external have been connected in a constraints file. My power supply positive terminal is hooked into the A0 port on my arty board, and the negative terminal is hooked into a gnd port. The XADC is attached to the AXI lite bus, controlled by the microblaze. Please let me know if any of this is unclear. P.S. I've looked into the
  8. @jpeyron, okay, thank you for the help! Best Regards, nystflame
  9. @jpeyron , I have since followed the steps outlined in the quad spi reference guide, and have had better success with transfers. Also, the core is configured in slave mode. I do have one main question now though.. Is the data transmit register double buffered? It doesn't say that it is in the IP quad spi reference guide, it only says the receive register is double buffered... It seems though that the transmit register loads two of the 16 bit half words that i'm trying to transfer.
  10. @jpeyron , Thanks for the info! I also managed to get the j6 header working... I hadn't made the correct pins external in the block designer and created the appropriate constraints file to attach the external pins to the physical pins on the header.
  11. Hello, I'm having some issues with multiple (16bit) transactions while holding slave select low. I'm using the example master polling spi code from the xilinx SDK, and have manual slave select working where it holds the SS line low while performing the multiple transactions, and once finish it goes high again. My issue is that i'm trying to make a simple slave which can write to a register continuously if it receives a write command from the master, and then if a read command is sent from the master, the slave will send back whatever is in the designated register requested by the master.
  12. Hi @jpeyron, I appreciate you looking into this with me. I look forward to what you find, and am looking into what you've posted. Still no luck on my end though. Regards, Nystflame
  13. Hello, I'm having trouble understanding how to address the J6 header on the Arty board. I've been able to interact with the GPIO registers to toggle other ChipKit shield pins as well as toggle all of the led's. When generating the project, I see that the base address for SPI in my project is at 0x44a00000 with high address being 0x44a0FFFF. I don't understand where in that memory the J6 header is, and am unable to find any resources with the answer. It might also be good to note that I generated the IP block by dragging and dropping the "SPI connector J6" from the Board section of the IP