Piasa

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  1. Audio processing

    There are three phases to this design. Phase 1 -- get the mic input to work at all. Phase 2 -- develop DSP algorithm for FPGA. Phase 3 -- implement and test. One thing you can try is getting the mic input into a file that you can use for testing DSP algorithms out. It is better to test out DSP on a computer first as the iteration time is much lower. You can also try DSP algorithms on voice recordings from the internet to get a basic idea of what processing might sound like. Finally, implementation. For this design, I suggest using a DSP48, a small RAM, and a small FSM. FIR filters are nicer as the fixed-point models are predictable and fairly easy. IIR filters are probably more applicable, but fixed point models could have more issues. In either case though, you are looking at generating coefficients in matlab/octave or something like that.
  2. FPGA based PWM generation

    This is not correct. For the ramp case it mostly works. The ramp is a test signal that minimizes the importance of the signed/unsigned input differentiation. The choice to invert the msb or not is based on if the input is signed/unsigned. A test signal that alternates between +1 and -1 would show this best. After all, if the msb is not inverted this would be 0x0001 to 0xFFFF vs 0x8001 to 0x7FFF. This is ~0% to ~100% vs ~50% to ~50%. Is this in comparison to a traditional PWM system or a traditional PDM system?
  3. FPGA based PWM generation

    I'm not entirely certain what your argument is. The PDM waveforms can be different when the 15 lsb of the ramp's first half do not match the 15 lsb of the ramp's second half. In that case, the values provided to the comparator will be different. The analog waveform should look similar, except for any DC offset (which is not possible with the AC-coupled input) or any phase shift (which is not visible without an external reference). --Added: I will answer the question I think is being discussed /wrt encoding. At a minimum, an input value (A) that is considered higher in value than a second input (B) should result in a higher density of the PDM output. sumOfOnesPerPeriod(A) > sumOfOnesPerPeriod(B). This is true for all encoding -- unsigned, signed 2's complement, signed 1's complement, zig-zag, etc... For unsigned, this property is automatic. For signed 2's complement, this becomes a simple operation of inverting the msb. For 1s complement this is a bit more difficult because 1's complement addition does have feedback from the msb to the lsb. For zig-zag this would be (i >>> 1) ^ -(i & 1) ^ 0x8000.
  4. FPGA based PWM generation

    First, VHDL doesn't define "+" for std_logic_vector. Second, VHDL (for numeric_std and std_logic_arith) defines size(A+B) = max(size(A), size(B)). "c<=a+b" would not be a synthesis error. This would be a logical error. Verilog is similar, but includes the LHS in the size calculation as well. Last, mod is defined differently for VHDL vs Verilog when negative numbers are used. That point is just a note. I haven't really looked at the FPGA implementation because it doesn't answer any interesting questions. It does not include the reconstruction filter and does not provide any estimate of the output spectrum. It also does not include the effects of finite rise/fall times or other driver imperfections.
  5. FPGA based PWM generation

    You can also pick up ~3 bits using oserdes and maybe 2 bits from a faster io clock.
  6. Do you have an example of a VHDL digital filter to filter noise?

    What does the entire system look like? DSP applications are much easier to implement on a computer. If the ADC is low-rate data, a CPU/GPU implementation might be much easier to do and also has the advantage of using floating point math. If the ADC is multichannel, you might consider adding a second ADC input that can be used as a noise reference. This can be used with and adaptive filter to remove the noise. If the sampling rate is fairly low, this could be done on the FPGA with normal adaptive filtering methods. The concept is that the spectral content of the noise reference is correlated to the noise in the main channel. If the data is post processed, you can also remove this from a single recording under some assumptions. If the fpga is to be used and the sampling rate is low, it still makes sense to serialize the operations for the filter to reduce resources. This can be done in different ways. The DSP48 slices and BRAMs can be used together to create a mini-dsp that executes a simple set of instructions. This is actually easier than it sounds as there doesn't need to be any branching or anything that is difficult in a normal CPU. Software pipelining is also easy to do. This is easier to do in VHDL, or with a script that generates the RTL for this application.
  7. Using the Rj45 and Ethernet controller

    I don't think you can access the PS* (ARM) pins from the PL (FPGA) section of the SoC. You likely need to have ethernet connected to the ARM.
  8. FPGA based PWM generation

    The system is AC coupled, so no dc output. You can directly use a 16b unsigned value if you consider yourself to have a 16b unsigned input. The DC component will be removed. If you consider yourself to have a 16b signed 2's complement input, you would need to invert the msb. Otherwise -1 would map to ~100% duty ratio, and -32k would map to 50%. (0 would map to 0% and +32k would map to ~50%). Inverting the msb has the effect of converting the 16b signed value into a 16b unsigned value that is equal to x + 32*1024. -1 maps to ~50%, -32k maps to 0%, 0 maps to 50% and 32k maps to ~100%. This design maximizes the number of transitions. Each transition has a cost in terms of parasitics in the circuit. The goal of maximizing transitions is to move more energy to higher frequencies that the RCRC filter can reject more easily -- the goal being to reduce ripple within a pwm period. There are other options. in terms of arranging the bits. You can also get 2x rate PWM signals or 4x rate PWM for example.
  9. FPGA based PWM generation

    Can you be more specific? For example, differences in comparisons can affect the design. IIRC the original blog post used "<=" and "<" in two different snippets. The difference between comparisons is either a small offset or a phase inversion or both.
  10. Channels in the XADC

    This is done using the sequencer. The continuous sequence mode, simultaneous sequence mode, or independent adc mode might be applicable. Continuous sequence requires you to configure the sequence for sampling data. The other two modes have a fixed sequence and might give you data from channels you do not care about. Chapter 5 also has more info on this.
  11. FPGA based PWM generation

    Sorry, I updated my post as you were typing this. The post now gives a more accurate description. The signed input must be converted into an unsigned "on-cycles per period." In this case, the design accomplishes this in the same way that signed values would be converted to offset binary.
  12. FPGA based PWM generation

    This does make sense if there is an error in the implementation. From my glance to the code the only issue is that the comparison prevents either the all 0 or the all 1 sequence (I don't recall which was not possible). That is independent of the bit-reversal. A simulation of a specific implementation is not helpful in illustrating the core concept though. The core concept can be explained without even giving a reference implementation. Both PWM and PDM expect some form of filter. In some cases this will be an RC filter, in some cases a LR filter, in some cases an RLC filter, and in some cases the load will have these properties already. Yes, this is correct. This is the "not all 1's are equal" comment. This method is similar to PDM in that there are many transitions. This makes it less suited for power amplifiers or when the output device cannot switch suitably fast. In this application, a signed value must be mapped into "number of cycles on per 2**N cycles". This is an unsigned value independent of if the input is signed or unsigned. The design assumes that a 1 output maps to +V and a 0 output maps to -V. To output 0V, the design would need to output an equal number of 0's and 1's. In this case, the number of cycles in the period is also related to the precision of the input. That is not required in general. However, for this case the operation to get from signed input sample to unsigned number of on-cycles is the same as the conversion from signed to offset binary.
  13. FPGA based PWM generation

    This thread is disturbingly long and often off topic. The premise is that, if a set contains 0 to 2**N - 1 it will have k elements less than k for any permutation of the set. (k < 2**N - 2) (the article has an off by one codeword issue IIRC) From there, a heuristic for choosing a sequence that maximizes high-frequency energy while maintaining the same average would be bit reversing the value of a counter. Bit reversing does not create random numbers, it mostly just moves the lsb to the msb which leads to an increase in max-frequency content. The effect of moving the 2nd lsb to the 2nd msb does this to a lower effect. There are legitimate concerns comparing PDM to PWM in a practical system. Slew-rates and other parasitics lead to a case where not all 1's are equal. This is true of any PDM system and are not unique to this approach. Likewise, there are concerns with comparing lower-rate PDM to a higher-rate PWM that results in the same number of transitions or uses the same switching energy of a power device. If you want to construct a case where this method is inferior to PWM you certainly can. It is not strictly inferior though. It should be better than the PWM version that has the same counter period and not better than an optimal PDM implementation -- assuming no output device imperfections. Also, why is VHDL/Verilog even being discussed? That is purely an implementation detail. Both languages work fine for this purpose and neither provides much insight into the topic. Octave/Matlab/etc.. or an analog circuity simulator would be more relevant. Also, why are binary formats being discussed? That is based on input to the P*M and how the P*M converts a codeword into an analog value.
  14. Dividing by 10....

    You can use the same method to divide by other constant values as well. It is just (2**32) * (1/n) or some desired power of two. The precision is based on how large the dividend can be as this defines when the rounding error becomes off by one. You can also do a similar trick in an FPGA for mod, at least for some cases. If you look at the fractional bits, there can be patterns that allow a few of the fractional bits to be used with a lookup table for the value of mod. This is based on the modulus and how large the argument can get.
  15. DDR3 mig 7 traffic control example on nexys video board

    I suggest adding a chipscope to see what is going wrong. There are some simple issues that can occur -- incorrect frequency for design, incorrect frequency for idelays, incorrect reset polarity, driving user signals before init is done, incorrect DCI configuration -- but it sounds like you have accounted for that. There are several reasons why init might not finish. the single IO on the component isn't enough to know what exactly is wrong.