Piasa

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Piasa last won the day on May 29 2018

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  1. I guess my statement isn't accurate. Mealy/Moore/Mendevev could all be written with two processes. I guess my real statement is that the single clocked process FSM is not what people want to write, logically. But the languages make this style common.
  2. How should the FSM should handle 8 7 0 1 1 8 8 8 7 0 1 7 8 7 0 0 0 1 7? 87011 is not 87017. 8887017 contains 87017. But if 8701 was seen before, the 87017 seen occurs after 8887. 8700017 conatins 870 and 17, but has two extra 0's. I don't think any FSM model allows async inputs that modify state. I've always found that Mealy is the FSM that devs want to write -- even when they write Moore/Mendevev FSMs. Mealy provides next-state/next-value logic -- often avoiding code duplication. But it uses more lines of code so it is rarely used. For this context, VHDL and V
  3. not sure what you are trying to do. You have 1Hz going into designated number which connects to 4 bit counter with a comment of "moore machine one cycle". The frequency divider has three outputs of which two go a decoder and a mux for reasons. The states also have names s0 to s5. The FSM seems to be "ignore input until a zero is seen, otherwise advance state". I don't see a relation to the diagram. I don't understand either the block diagram or the problem description or the proposed code. You need to specify the problem in a more understandable format or post this to a forum that h
  4. Piasa

    Array

    Verilog has generate as well, but it is a bit different in the nested generate case. Also, make sure that the area/time trade-off makes sense. The goal is to describe a system that solves your problem. If you need to add 1000000 numbers, maybe you can add 100 at a time and solve the problem over several cycles.
  5. For FPGAs, take the input and make a bit-reversed version. This can be done with a function in VHDL -- reverses a std_logic_vector and returns a value with the same range as input. function reverse(x : std_logic_vector) return std_logic_vector is variable xnml : std_logic_vector(x'length-1 downto 0) := x; variable rev : std_logic_vector(0 to x'length-1); variable result : std_logic_vector(x'range); begin for i in xnml'range loop rev(i) := xnml(i); end loop; result := rev; return result; end function; -- find leftmost 1 and return a 1 hot version function leftmost(x
  6. This is a fun and short post on how addition/subtraction can be used for logic and not just numbers. The example I use is "x & -x". This expression takes a vector, finds the rightmost 1 and sets all left bits to 0. The right bits are already 0. If the input is 0, the expression returns an all 0 vector. Thus the expression either gives a 1-hot vector of the rightmost 1, or gives 0 if there is no bit set to 1. There are a lot of interesting expressions. But some are imperfect for use. For example "x | (x-1)" will find the rightmost 1 and set all bits to the right to 1. But i
  7. You want to use an MMCM or clocking IP core of some form in order to get a 104MHz clock that can be used to get 1000MSPS vs 25/26ths that rate.
  8. You can also import just "+" and "-" from std_logic_signed as well as the conversion functions from std_logic_arith. This way you still are required to specify signed/unsigned for "<", "*", etc... Importing "-" from std_logic_signed will give you the unary "-", which can be used for logical induction in expressions like (-x) and (x).
  9. You might be re-inventing the tree. j/k. FPGAs have async fifo's as hard IP. They also have vendor supplied IP generators. For xilinx, the "primitives guide" has more info. There is also coregen. Someone also mentioned there is a new way to create generic fifo's that isn't the very-limited unimacros. A properly constrained design will ensure that the skew between bits in this bus will be less than one other-clock cycle. In newer Vivado, there is a constraint for this specifically. In older versions of Vivado and all of ISE, the bus was simply constrained to arrive to the ot
  10. Probably not. You just need to be aware that the register outputs have some delay from the logic that is in the register file. Registering outputs is "generally good" design. However, it isn't always needed or possible. It is up to you to decide the logical impact in this case and then compare against any performance benefits.
  11. "Last signal assignment wins". I'm not sure if you are pointing out that I missed a word or if you are questioning the LRM.
  12. Y There are several common things that should result in this. Linked-lists are one example, but there are probably a dozen others. Of course that is off topic from a code review of a register file for a cpu that doesn't currently have a C/C++ compiler.
  13. Just realized I didn't respond to this yesterday. By infrastructure, I mean clocks and general resets that are used at startup or otherwise not used during normal operating conditions. The distributed memory approach was presented a few posts up. It doesn't make sense for your goal of an easy to read, general implementation. In many designs, it is preferred to have output registers. This does add the 1 register delay. In some cases the unregistered outputs are unavoidable. When possible, having output registers is nice because the longest path won't be half in one file and h
  14. BRAM does, but then you can't read in the same cycle. A Xilinx targeted register file could use DMEM. This requires four copies of each register for the 4-6 read/cycle case, or two copies for the 1-3 read/cycle case. The DMEM have a 3-read, 1-write config. To get 4-6 ports means two copies. To get the two writes again means two copies and the addition of a small tag ram which can be implemented using registers. It is debatable if this is that much better as both should be small for modern FPGAs. It removes the input muxes for the priority logic as portA now only writes to two DMEM
  15. I think in this case the priority logic is hard to remove in a way that isn't worse. Some (or all?) synthesis tools will ignore 'x' and '-' and instead replace them with '0'. This can add some extra logic to do something you specifically didn't care about. Also, I agree that small sandbox designs can be really fun and informative. IMO, devs tend to underestimate the FPGA in some ways which results in excessive pre-optimization.