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  1. Hi @Jpeyron, Maybe I did not express myself well. It is clear how the pmodad1 is interfaced with the GPIO. I verified the above design with a PmodAD1. But what is not clear is how I am going to connect the following I/O ports: (Or should I interface those ports with the GPIO and control them with the help of the processor? I mean a similar connection between the led (15: 0) of the pmodad1 block and the input port gpio_io_i (15: 0) of the GPIO module. If yes, then this will answer my question.) Address: in std_logic_vector(7 downto 0); DataIn: in std_logic_vector(7 downto 0); DataOut: out std_logic_vector(7 downto 0); Read: in std_logic; Write: in std_logic; DataRdy: out std_logic; In the Nexys 3 those ports were driven by the Epp module. Thanks! F
  2. Hi @Jpeyron, I went ahead and I followed your recommendations regarding the zybo approach. I added the PmodSF.vhd as a block in Vivado and I made the following I/O ports as externals: 1- P1 (out)  SEL 2- P2 (out)  SDI 3- P3 (in)  SDO 4- P4 (out)  SCK Now my questions are the following: 1) How should I interface the following ports of the PmodSF with the axi_gpio? Address: in std_logic_vector(7 downto 0); DataIn: in std_logic_vector(7 downto 0); DataOut: out std_logic_vector(7 downto 0); Read: in std_logic; Write: in std_logic; DataRdy: out std_logic; 2) Which gpio functions do I need to read/write/erase and program the PmodSF from the Zynq Processor? Thanks! Regards, F
  3. Hi @jpeyron, Thank you for your answer. In a first step I will go for the zybo approach, but later I would like to read and write to the Pmodsf from the Microblaze. 1- Do you think it could make sense to build a FSM in Verilog/VHDL, in order to drive EPP/PmodSF ports? Then, I could store the results of a read/write operation in a register accessible to the Microblaze. 2- Or would it be much simpler to use a Xilinx IP (axi_SPI) to directly drive the I/O ports of the PmodSF? If yes, where can I get the driver code of that PmodSF for the microblaze (C code). Once again thanks! Regards, F
  4. N.B: I have also a basys3 with me, in case it might be more suitable with that one. F
  5. Hi @jpeyron, The EPP module of that design has many I/O ports which are connected to some pins of the Nexys3. My question is the following : Where should I tie all those pins in the zybo or spartan6lx9 ? Thanks! ## onBoard USB controller Net "EppAstb" LOC = H1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L41N_GCLK26_M3DQ5, Sch name = U-FLAGA Net "EppDstb" LOC = K4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L42P_GCLK25_TRDY2_M3UDM, Sch name = U-FLAGB Net "EppWait" LOC = C2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L83P, Sch name = U-SLRD Net "EppDB<0>" LOC = E1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L50N_M3BA2, Sch name = U-FD0 Net "EppDB<1>" LOC = F4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L51P_M3A10, Sch name = U-FD1 Net "EppDB<2>" LOC = F3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L51N_M3A4, Sch name = U-FD2 Net "EppDB<3>" LOC = D2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L52P_M3A8, Sch name = U-FD3 Net "EppDB<4>" LOC = D1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L52N_M3A9, Sch name = U-FD4 Net "EppDB<5>" LOC = H7 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L53P_M3CKE, Sch name = U-FD5 Net "EppDB<6>" LOC = G6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L53N_M3A12, Sch name = U-FD6 Net "EppDB<7>" LOC = E4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L54P_M3RESET, Sch name = U-FD7 Net "UsbFlag" LOC = F5 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L55N_M3A14, Sch name = U-FLAGC Regards, F
  6. Dear digilent, I am interested to retarget the following design to a zybo or spartan 6 FPGA. The design link is: https://reference.digilentinc.com/reference/pmod/pmodsf/start ( Nexys 3 VHDL Example - ISE 13.4 ). Could you please advise me how to do it? Thank you. F