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  1. Hi All, I just wanted to say that I'm also really struggling to get any kind of TFTP boot going on the Zynq, but not with other devices that I have. I have another ARM-based SBC computer, the S805X "La Frite" Librecomputer, which also boots via U-boot. I connected its ethernet port to a physical internal network consisting of a switch and a router (Router is the "HAp ac lite" from MikroTik), which is running DHCP. I connect my laptop to it running TFTP server, and is serving a very dumb "test.txt" file consisting of 16 bytes. I can load it from the La Frite librecomputer by simply se
  2. Hi Wyllyam, It appears I have the "Rev C" variant. I have attached an image of my ZedBoard setup together with all the jumper settings incase it is useful.
  3. Hi everyone, I am using a ZedBoard, and following this guide: I succesfully got to Chapter 2, where I can do the following: Create Zynq block design Export hardware file (.xsa) Use Vitis to create a "standalone hardware platform" using this file Use Vitis to create a Hello World application Debug this application, and I can see "Hello World" printed in Vitis serial monitor over the UART cable. However, I would like to progress to running Pe
  4. Hi, I recently discovered that the wrong scan codes are sent for certain keys. This is tested with my own PS2 keyboard controller, and the same behaviour is present with the official demo: I have tested two keyboards: One Logitech K120, and one Microsoft comfort curve 3000. The following behaviour is exhibited: Left arrow set 2 scancode should be: E0 6B / E0 F0 6B. Actual: 6B / F0 6B Up arrow set 2 scancode should be: E0 75 / E0 F0 75. Actual: 75 / F0 75 Down arrow set
  5. Thank you all for your helpful comments, Indeed, on page 100 of UG 471: "7 Series SelectIO" I found the following table: It appears that 0.9V is the VREF configuration that should be used with SSTL18_II (be it INTERNAL or not).
  6. Hi, I am in the process of developing my own DDR2 controller as an exercise. Consequently, I'm trying to avoid using tools like MIG. Unfortunately I could not fully escape the clutches of automated tools, as in order to correctly configure the .xdc constraints file, I've had to have a peek at the following .prj file generated by the MIG in the official Digilent DDR2 Demo implementation: I interpret the following line: "<InternalVref>1</InternalVref>" as setting the INTERNAL_VREF property to 1V. The
  7. Hi, I am using Vivado 2016.4 to program the Nexys4 DDR 7-segment display. I have a very simple VHDL project, which works as follows: 100 MHz clock is used to increment an 8-bit counter when this counter overflows, it inverts the value of a local signal called "slowclk". Hence, "slowclk" is "clk" divided by 512. the "slowclk" is used to increment another 8-bit counter, the output of which is assigned to the 7-segment display segment selector pins on the board. Complete VHDL source: Note: I understand that given such division, the effect on the digit segm