Patrick Lehmann

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About Patrick Lehmann

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  1. In the board description for the ArtyS7, it's written to have a 12 MHz system clock at pin F14. That's not correct. Schematic revision E.1 for ArtyS7 is showing IC2 is open => no clock at all IC2 is - if soldered - a 100 MHz clock => ASEM1-100.000MHZ-LC-T As also discovered by the author of the board description, 12 MHz is a useless clock for 7-series FPGA,s because it's to slow for clock modifying blocks (PLL, MMCM, ...) The trace 12MHz/UCLK has a R0, but no source in schematics (incomplete schematics or an open trace ...) As a summary: the ArtyS7 board has o
  2. Hello, some people might already know The PoC-Library. It's a collection of over 120 free and open source IP cores, that are platform independent. The IP core work on Altera, Intel, Lattice and Xilinx FPGAs of any device family. The core are describe in platform independent, generic VHDL code. If vendor primitives are required or better implementations can be achieved, a configuration mechanism will select a suitable implementation. PoC has gotten a first simple set of new I/O controllers abstracting Digilent's Pmods. These are located here: https://github.com/VLSI-EDA/PoC/tree/mas