guneryunus

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  1. thank i will use <> .I want to put all the values in order. I need to do this bit by bit.dac works in series
  2. i want to generate sine wave on dac (pmodda3)(http://www.analog.com/media/en/technical-documentation/data-sheets/AD5541A.pdf)and i am using spartan3e but there ara several warnings ,How can i fix the warnings? i loaded code and picture. help me please ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; use ieee.numeric_std.all; entity kecelikalem is port( clk: in STD_LOGIC; reset : in STD_LOGIC; din:out std_logic; ldac:out std_logic:='1'; cs :out std_logic:='1'; sclk :out std_logic:='1'); end kecelikalem; architecture Behavioral of kecelikalem is signal a:integer range 0 to 3:=0; signal i : integer range 0 to 18:=0; type veri is array (2 downto 0) of std_logic_vector(15 downto 0); signal sine :veri:=("1100000000100000","0000000000001111","1100000000000000"); --signal sine :std_logic_vector(15 downto 0):="1100000000000011"; signal data :std_logic_vector(15 downto 0); signal temporal: STD_LOGIC; signal counter : integer range 0 to 124999 := 0; begin frequency_divider: process (reset, clk) begin if (reset = '1') then temporal <= '0'; counter <= 0; elsif rising_edge(clk) then if (counter = 124999) then temporal <= NOT(temporal); counter <= 0; else counter <= counter + 1; end if; end if; end process; sclk <= temporal; process (temporal) begin if falling_edge(temporal) then if(a=3) then a<=0; else data<=sine(a); if (i=18) then a<=a+1; ldac<='1'; i<=0; else if (i=17) then ldac <='0'; else if (i=16) then cs<='1'; ldac <='1'; else cs<='0'; din<=data(i); --din<=sine(i); ldac <='1'; end if ; end if; end if ; i<=i+1; end if; end if; end process; end Behavioral;
  3. again i wrote codes you can see easly figure library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; use ieee.numeric_std.all; entity kecelikalem is port( clk:in std_logic; din:out std_logic; ldac:out std_logic:='1'; cs :out std_logic:='0'; data_taken : out STD_LOGIC := '0'; sclk :out std_logic:='1' ); end kecelikalem; architecture Behavioral of kecelikalem is signal i : integer range 0 to 15; --type veri is array (0) of std_logic_vector(15 downto 0); signal sine :std_logic_vector(15 downto 0):="1100000000000001"; signal sclk_state : std_logic_vector(1 downto 0) := "00"; begin --SCLK <= sclk_state(1); --ldac <= '0'; --cs<='1'; sclk<=clk; process (clk) begin if rising_edge(clk) then data_taken <= '0'; case sclk_state is when "00"=> sclk_state<="01"; -- register kaydırma ldac<='1'; cs<='0'; din<=sine(i); i<=i+1; --if (i=15) then --i<=0; --end if ; when "01"=> sclk_state<="10"; cs<='1'; when "10"=> sclk_state<="11"; ldac<='0'; when others => sclk_state<="00"; end case ; end if; end process; end Behavioral;
  4. i am using ise 14.7 and the speed is 50 mhz. my dac is working in series
  5. i want to generate sine wave on dac (http://store.digilentinc.com/pmod-da3-one-16-bit-d-a-output/) i am using 16 bit dac and i am using spartan 3e . i cant do it . help me ?? library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity pmod_da3 is Port ( clk : in STD_LOGIC; CSn : out STD_LOGIC; LDACn : out STD_LOGIC; SCLK : out STD_LOGIC; SDAT : out STD_LOGIC; data_taken : out STD_LOGIC := '0'; level : in STD_LOGIC_VECTOR (15 downto 0)); end pmod_da3; architecture Behavioral of pmod_da3 is type array_type is array (0 to 1 ) of std_logic_vector(15 downto 0); signal array_name :array_type:=("0000000000000001","0000000000000011"); constant len : integer := 19; signal CSn_shift_reg : std_logic_vector(len-1 downto 0) := (len-17 downto 0 => '1', others => '0'); signal LDACn_shift_reg : std_logic_vector(len-1 downto 0) := (1 => '0', others => '1'); signal SDAT_shift_reg : std_logic_vector(len-1 downto 0) := (others => '0'); signal sclk_state : std_logic_vector(1 downto 0) := "00"; begin SCLK <= sclk_state(0); LDACn <= LDACn_shift_reg(0); CSn <= CSn_shift_reg(0); clk_proc: process(clk) variable a: integer range 0 to 15; begin if rising_edge(clk) then data_taken <= '0'; case sclk_state is when "00" => sclk_state <= "01"; -- Mpve the shift regeister along SDAT <= array_name(a); a:=a+1; if (a=15) then a:=0; end if; -- SDAT_shift_reg <= SDAT_shift_reg(len-2 downto 0) & 'X'; LDACn_shift_reg <= LDACn_shift_reg(len-2 downto 0) & LDACn_shift_reg(len-1); if LDACn_shift_reg(1) = '0' then SDAT_shift_reg(SDAT_shift_reg'high downto SDAT_shift_reg'high-level'high) <= level; data_taken <= '1'; end if; when "01" => sclk_state <= "10"; when "10" => sclk_state <= "11"; CSn_shift_reg <= CSn_shift_reg(len-2 downto 0) & CSn_shift_reg(len-1); when others => sclk_state <= "00"; end case; end if; end process; end Behavioral;