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  1. Hi, I also solved the problem of the mapping of the signal ac_bclk, which was mapped to pin K18, the same pin as the signal btns_4bits_i[0]. I didn't change the mapping of ac_blck because on the schematics ( the K18 pin is dedicated to this clock. But I saw also on the schematics that btns_4bits_i[1] and btns_4bits_i[3] were mapped to the pins names BTN1 and BTN3, but btns_4bits_i[0] and btns_4bits_i[2] were not. I assumed that this was an error and mapped those signals to BTN0 and BTN2 respectively.
  2. Hi, I recently purchased a Zybo board and used the DMA Audio Demo ( to acquire audio input and output. The Audio codec records 5 seconds of audio and then passes it to the Zynq PL via I²S protocol, that is it transmits the bit clock BCLK, the word select RECLRC and the data recorded RECDAT. My goal is to take this data and apply a filter on it, before the stream is mapped into memory with a DMA and then sent back to the audio codec and played in earphones. But I don't really understand how th
  3. Hey, If you managed to change your project in order to process audio in real time instead of record and playback, I would be interested in knowing how you did it ! If you can share some files and tips, it would be great Lucile
  4. Solved the problem by creating a new Hardware Platform Specifiation (with the design_1_wrapper.hdf file), a new BSP based on this platform and a new application where I copied the c files. Thanks for your help !
  5. Hi @artvvb, I now launched the project in SDK as said in the tutorial, but it fails to generate the BSP sources, even if I click on "regenerate bsp sources" as you told me. Here's the error I get : 10:02:56 INFO : Launching XSCT server: xsct.bat -interactive C:\Users\Lucile\Zybo-DMA-5essai\Zybo-DMA\proj\DMA.sdk\temp_xsdb_launch_script.tcl 10:02:56 INFO : XSCT server has started successfully. 10:02:56 INFO : Successfully done setting XSCT server connection channel 10:02:56 INFO : Successfully done setting SDK workspace 10:02:56 INFO : Registering command ha
  6. @artvvb I am using Vivado 2017.2. Thanks @jpeyron, I saw it yesterday, but yesterday I didn't work because when opening the design_1_bd.tcl file AFTER creating the project, the version was updated to 2017.2 but the changes weren't (I guess) taken in account everywhere. Today I tried it again by changing the version BEFORE creating the project, and was able to generate the bitstream. Thank you both for your help ! Lucile
  7. Hi, I started again from the beginning and updated the IPs as you said. The Output products were then generated. When I try to generate the bitstream, I still got many errors : [BD 41-1665] Unable to generate top-level wrapper HDL for the BD-design '' is locked. Locked reason(s): * Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue. List of locked IPs: design_1_axi_dma_0_0 design_1_auto_pc_0 design_1_processing_system7_0_axi_periph_0 design_1_processing_system7_0_0 design_1_axi_mem
  8. Hello, I just received my Zybo board, and I would like to use the DMA Audio demo to have audio input and output ready-to-run on my board. I chose to put the project into Vivado to be able to see the block design and make changes in the design later on. I did the following steps : - Downloaded the ZIP archive you can find on - Created the project with TCL command and create_design.tcl file - Opened block design by adding the BD file as a design source in Vivado - Added the d_axi_i2s_audio