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Posts posted by theUltimateSource

  1. UART are connected to pins that cannot be accessed by PL. You could use a USB-TTL chip. 

    As a side note, I am missing the reference to the FTDI on the zybo_sch.pdf... or at least a reference to connector J11. Took me a while to find the uart pins


  2. I think there is a confusion. I am not talking about IO buffer (i.e., "physical ports") here. A port list is a list of inputs and outputs of your module as you declared here:

    1 hour ago, yassinema2018 said:

    module pwm( input clk, input enable, output pwm_out, input [31:0] pwm_val, input [31:0] pwm_period );

    Vivado needs a top module. The top module contains a port list that Vivado is going to wire to physical pins. Your top module is pwm that's why Vivado does what it did. Instead, use a top module that instantiates axi and pwm like so:

    top_module (
        output pwm_out,
        inout DDR_...
        inout FIXED_IO...

    Vivado tries automatically to figure out which is your top module. If you have more than one hierarchie it picks whatever. In this case you can manually tell Vivado which your top module is.


    To put it simple: remove all inputs and outputs in your top module that you don't want Vivado to wire at pins.

  3. 2 minutes ago, yassinema2018 said:

    vivado tries to assign a physical port to each of the 64 bits and that's the problem because i don't need hardware ports to be assigned to them

    You are correct, you need to declare your module entity, instantiate the module, instantiate the axi interface and map the signals to your port lists. 

    I think these instructions here show you exactly what you are trying to do. It uses 4 PWM signals instead of one but is very easy to adjust. 

  4. did you use Vivado/Tools/create and package new IP as a starting point? It generates the axi wrapper for you. Instantiate your module and connect registers to axi.


    Again, your error log let's me assume something is wrong with your module.

  5. the problem is in your source file.

    If you want to synthesize your design you have to fix:

    • A LUT 'cnt2_i_2' is driving clock pin of 11 registers.
    • Number of unplaced terminals (64) is greater than number of available sites (50)

    otherwise it will only work in simulation.

  6. Hello, just plugged in my new Zybo Z7 471-015 but cannot connect to serial port. It works on the Zybo. 

    • PROG UART is connected to USB PC
    • BSP stdin, stdout is set to ps7_uart_1
    • I have no other application open that is accessing the serial ports
    • to make sure I dis- and reconnected the Zybo Z7, still doesn't appear on the port list
    • Zybo Z7 appears as USB Serial Converter A and B in the device mngr
    • restarted PC
    • tried another USB port
    • replaced USB cable, both are data cables
    • JP6 is set to USB
    • JP5 is set to JTAG
    • drivers had been installed with Vivado 2017.2
    • re-installed Vivado 2017.2 cable drivers, restarted PC


    USB port should be listed even without any PL configuration loaded, right?

  7. The pixel clock is directly derived from the video input, TMDS CLK. One character is 10 bit. Since it is DDR your pixel clock is 5 times lower than the serial, i.e., bit clock.

  8. hello,

    My new board just arrived yesterday :)

    I received my Zynq Development Voucher with instructions:

    1. log in to xilinx
    2. confirm your purchase and license entitlement placed into my account, code may only be used once
    3. generate FLEX license for product. Must be redeemed within one year of purchase

    I want to wait for a future release of Vivado before I use the license. So according to instructions, I need to perform steps 1 + 2, and wait until that release before generating the license. 

    Is this correct? Just want to be sure before messing something up :)

  9. On 03/08/2017 at 8:27 AM, M24 said:

    can you be more specific?

    what error messages do you get when programming the board?

    It shows error messages to help you identify the problem. Without them it is hard to find out what's wrong, not just for you but also for others trying to help... ;)

  10. I could observe that the SDSoC project does indeed have the file '720p_edid.txt' in the release folder. It gets deleted somehow during compilation. I copied it back in place before compilation finished and was able to generate the sd_card files that way.

  11. @RaulRB : you'r right, I moved the workspace to another location. 

    I created the platform again this time with the include folder (arm-xilinx-eabi). It did not work, however: when I create a new project with the basic example of the platform I still need to copy the header files manually to the project:

    D:\SDSoC\ddd\Release>C:\Xilinx\SDx\2017.1\llvm-clang\win64\llvm\bin\clang.exe -I../src -Wall -fmessage-length=0 -MMD -MP -D __SDSCC__ -target arm-none-eabi -mcpu=cortex-a9 -mfpu=vfpv3 -O0 -g -I C:/Xilinx/SDx/2017.1/target/aarch32-none/include -I C:/Xilinx/SDx/2017.1/Vivado_HLS/include -IC:/Xilinx/SDx/2017.1/SDK/gnu/aarch32/nt/gcc-arm-none-eabi/lib/gcc/arm-none-eabi/6.2.1/include -IC:/Xilinx/SDx/2017.1/SDK/gnu/aarch32/nt/gcc-arm-none-eabi/lib/gcc/arm-none-eabi/6.2.1/include-fixed -IC:/Xilinx/SDx/2017.1/SDK/gnu/aarch32/nt/gcc-arm-none-eabi/arm-none-eabi/include -IC:/Xilinx/SDx/2017.1/SDK/gnu/aarch32/nt/gcc-arm-none-eabi/arm-none-eabi/libc/usr/include -emit-llvm -S D:/SDSoC/ddd/src/arraycopy.c -o D:/SDSoC/ddd/Release/_sds/.llvm/src/arraycopy.s
    D:/SDSoC/ddd/src/arraycopy.c:38:10: fatal error: 'xgpio.h' file not found
    #include "xgpio.h"


    D:\SDSoC\ddd\Release>exit /b 1
    ERROR: [SdsCompiler 83-5005] clang exited with non-zero code processing D:/SDSoC/ddd/src/arraycopy.c
    sdscc log file saved as D:/SDSoC/ddd/Release/_sds/reports/sds_arraycopy.log
    ERROR: [SdsCompiler 83-5004] Build failed

    make: *** [src/arraycopy.o] Fehler 1

    note: this error dissappears after copying the required header files, so I can go around this for now...


    but I am facing an even bigger problem:

    I tripple-checked that I copied 720p_edid.txt to the right location. After platform creation this file was included as well. The platform generated in the 'release' folder of my SDSoC project is missing that file!

    ... This may take some time to complete
    CRITICAL WARNING: [Project 1-19] Could not find the file 'D:/SDSoC/ddd/Release/_sds/p0/ipi/zybo_hdmi_in.srcs/sources_1/bd/zybo_hdmi_in/ipshared/050c/src/720p_edid.txt'.

    ERROR: [Synth 8-3302] unable to open file '720p_edid.txt' in 'r' mode


    I even referenced the file to the sources of the vivado project, before creating the platform - no difference.


  12. SDSoC 2017.1 complains about an outdated file structure. I successfully created a new platform as in UG1146.

    Appearantly I missed one step since the header files had not been included. I added the custom platform and created a new project with the arraycopy sample.

    After manually adding xgpio.h it completes building. but when I enable create bitfile, create sd card it takes forever to compile and ends with errors.

    I'll try and create a new fsbl...