FarmerJo

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  1. Hi, I have a Zybo board and am using Vivado 2017.2. I have successfully written a number of VHDL modules allowing me to access the boards push-buttons, LEDs and slide switches using only the PL part of the device. I wondered if it was all possible to drive the LD_MIO LED from the FPGA? From my understanding it should be possible using the EMIO but have not been able to find an example or tutorial that shows how it is done. Regards FarmerJo
  2. Hi jpeyron, Many thanks for the links. Will have a good look at these. Regards FarmerJo
  3. Thanks for your reply Bianca. I am trying to do this as part of an exercise in learning about MicroBlaze, AXI interfaces, AXI timers/UART IP and the FPGA resources in general. I am using the Zybo because it is what I have at hand. The tutorial that you reference I have already been through in several variations but for now a hello world program using only the FPGA is what I would like to achieve. Regards FarmerJo
  4. Hi, I am using Vivado 2017.2 to create a project that uses a MicroBlaze soft CPU core system for a Zybo development board. The intended hardware design will be enough to be able to create a simple hello world program using the SDK. There will be UART and evuntually some GPIO to interface with the boards LEDs and switches etc. I start by adding a MicroBlaze IP to a blank block diagram. Then I run Block Automation and accept the default settings. In the TCL console I get the following info message. INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI What does this mean and do I need to do anything to correct this? Any help would be appreciated. Regards FarmerJo
  5. Hi artvvb, Thanks for the replies. Unfortunately I am in the process of learning VHDL and have no experience with Verilog at all. I have carefully read your advice and so far come up with the following code for section 4.3) -- Add user logic here -- simple counter process(S_AXI_ACLK) variable counter : integer := 0; begin if(rising_edge(S_AXI_ACLK)) then if(counter < (PWM_COUNTER_MAX-1)) then counter := counter + 1; else counter := 0; end if; end if; -- comparator statements that drive the PWM signal if(counter < slv_reg0) then PWM0 <= '1'; else PWM0 <= '0'; end if; if(counter < slv_reg0) then PWM1 <= '1'; else PWM1 <= '0'; end if; if(counter < slv_reg0) then PWM2 <= '1'; else PWM2 <= '0'; end if; if(counter < slv_reg0) then PWM3 <= '1'; else PWM3 <= '0'; end if; end process; The first part which defines the counter and increments it, is not showing any problems in Vivado (2017.2), however the second part, where PWM0 to PWM3 are assigned is causing an error which I can understand but cannot see how to resolve. The problem to me is that counter is a variable but slv_reg0 (slv_reg1, slv_reg2 and slv_reg3) are signals and the comparison (<) is not compatible. Any help to resolve this would be appreciated. My section 4.1 code is as follows. -- Users to add parameters here constant PWM_COUNTER_MAX : integer := 1024; -- User parameters ends And my section 4.2) code is as follows. -- Users to add ports here PWM0 : out bit; PWM1 : out bit; PWM2 : out bit; PWM3 : out bit; -- User ports ends Please advise if there appears to be a problem here. Regards FarmerJo my_pwm_ip_v1_0_S00_AXI.vhd
  6. Hi, I am running through the Creating a Custom IP core using the IP Integrator tutorial using Vivado 2017.2 and have run into a number of problems as follows. In section 4.1) Adding the the line, parameter integer PWM_COUNTER_MAX = 1024, Causes Vivado to mark the line with the warning, Warning: syntax error near "Integer". In section 4.2) Adding the lines, output wire PWM0, output wire PWM1, output wire PWM2, output wire PWM3, Causes Vivado to mark the first line with the warning, Warning: syntax error near "wire". In section 4.3) Adding the line, reg [15:0] counter = 0; Causes Vivado to mark the first line with the warning, Warning: syntax error near "15". Adding the remainder of this section causes a number of errors reporting that has not been declared. I have attached the VHDL file that I am working on. Any ideas why I am getting these issues? Forgive me as my VHDL is not very good at the moment and the issues I am having are probably only minor. Regards FarmerJo my_pwm_core_v1_0_S00_AXI.vhd
  7. Hi Jon, Appreciate the changes you made to the tutorial. Will try the changesto the Phy this way shortly. Regards FarmerJo
  8. Hi Jon, I will also be running through the "Creating a Custom IP core using the IP Integrator" tutorial using Vivado 2017.2 and will let you know if this works shortly. Have run through most of the other tutorials and no problems so far. Regards FarmerJo
  9. Ran through the tutorial but still did not work. Tried the three XSCT Console commands where the link speed was manually set and it worked as expected. Thanks and Regards FarmerJo
  10. Hi Jon, I am using version 2017.2 of Vivado which I used to run through the Getting Started with Zynq tutorial (but did not spot the Getting Started with Zynq Servers tutorial) which I will run through shortly. Will also look into link speed suggestion. Thanks for the quick reply. Will report back soon. Regards FarmerJo
  11. Hi, In the SDK I have created the lwIP echo server project which builds OK. I have connected the Zybo to my laptop which has an IP address of 192.168.1.1 and subnet 255.255.255.0. Without using telnet or putty initially the terminal output is as follows. -----lwIP TCP echo server ------ TCP packets sent to port 6001 will be echoed back Start PHY autonegotiation Waiting for PHY to complete autonegotiation. Auto negotiation error Phy setup error Assert due to phy setup failure I have also tried to connect using putty before this timeout occurs but still unable to get echo functionality. I have checked in my Vivado project and can see that ENET0 is enabled and ENET1 is disabled. Is this correct? The project README.txt file mentions a couple of assumptions that it makes. That a timer interrupt is connected to the interrupt controller and that all ethernet peripherals accessible from the processor can be used with lwIP. How do I verify that these two requirements have been met? Other than that, any ideas why this does not work? (I have an ultrazed-eg board and the echo server works OK for that). Regards FarmerJo
  12. Hi jpeyron, Many thanks for the quick answer. What are the Zybo-Z7-10 and Zybo-Z7-20 used for then? FarmerJo
  13. Hi, I am using Vivado Design Suite 2017.2 and have installed the board definitions files for the Zybo development board. From the silk screen the board is marked as Rev B. When I create a new project in Vivaldo, for Default Part, I select the zybo-z7-10 since the board uses a Z-7010 device. In am able to follow through the Getting Started with Zynq tutorial on the Digilent web site. However, the hello world program does not output any text to the terminal. If in Vivado I double click the Zynq7 IP I notice that in Clock Configuration|Basic Clocking I see that Input Frequency (MHz) is set to 33.333333. According to the schematic for the Zybo the PS clock frequency is 50MHz. Next I re-create the Vivado project but this time I set the Default Part to Zybo. If I now double click the Zynq7 IP I see in Clock Configuration|Basic Clocking that the Input Frequency (MHz) is now 50. I now get the expected hello world output also. Which Default part should I be using for my Zybo board? Also I have done some silimar work for a ultrazed-eg board, where only the PS part was used. In this case I did not need to downlolad the bitstream. But in order for the Zybo project to work with the switches, push buttons and LEDs it needed the bitstream downloaded before it would work. Why is there a difference between the two boards? Regards FarmerJo