Hi all. I would like to ask you a question regarding the RAM/DDR controller of the Nexys4DDR.
I would like to access (IP parameters in the MIG as in https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-user-demo/start ) the ddr memory whose component is shown below using a 16b width data.
For this, if I am correct, the address is handled RANK_BANK_ROW_COLUMN.
So I do not understand why in the provided code from Mihaita Nagy they create the user_interface address like these
mem_addr <= ram_a_int(26 downto 4) & "0000";
Here, mem_addr has 27b width.
Similarly, I wonder why in the ram control the mask and the read data uses the following LSB and not the MSB of the address:
case(ram_a_int(3 downto 1)) is
when "000" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(15 downto 8) &
mem_rd_data(15 downto 8);
...
Would not it be more sense to store the 16b words contiguously, starting at the address 0?
and if so, how would the vhdl code look like?
Thank you very much for your time, and regards.
The component used looks like
component ddr_xadc
port (
-- Inouts
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
-- Inputs
sys_clk_i : in std_logic;
sys_rst : in std_logic;
-- user interface signals
app_addr : in std_logic_vector(26 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(127 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(15 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(127 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_sr_active : out std_logic;
app_ref_req : in std_logic;
app_ref_ack : out std_logic;
app_zq_req : in std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
-- device_temp_i : in std_logic_vector(11 downto 0); -- not used, inside the core
init_calib_complete : out std_logic);
end component;
