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Nexys4 DDR DDR2 Memory Interface

2fmu replied to 2fmu's question in FPGA

@[email protected] Thank you very much. I will look for it in the DDR2 documentation.
2fmu reacted to an answer to a question: Nexys4 DDR DDR2 Memory Interface July 25, 2017
Nexys4 DDR DDR2 Memory Interface

2fmu posted a question in FPGA

Hi all. I would like to ask you a question regarding the RAM/DDR controller of the Nexys4DDR. I would like to access (IP parameters in the MIG as in https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-user-demo/start ) the ddr memory whose component is shown below using a 16b width data. For this, if I am correct, the address is handled RANK_BANK_ROW_COLUMN. So I do not understand why in the provided code from Mihaita Nagy they create the user_interface address like these mem_addr <= ram_a_int(26 downto 4) & "0000";