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  1. Hello @elodg, many thanks for the information! The length (in picoseconds?) is equal for all rx wires and for all rx wires. For me it remains unclear if C23 (22pF to GND) adds an delay to eth_rxck or not. Many thanks in advance! Jens
  2. Hello Jon, could the layout engineer already have a look at this topic? Thanks a lot! Jens
  3. Hello, since one can see only a small amount of the routed wires on the PCB top and bottom layer the only confident source of the delay values is the PCB layout. In this case, the absolute delays are not of interest but the difference in delays between the data lines and clocks (rx and tx). The delay of the rx-clk-line may also be influenced by C23 (22pF to GND). Jens
  4. The "Nexys Video™ FPGA Board Reference Manual" (Revised May 30, 2017) describes in Table 9 (page 20) the "Recommended usage" of the pins of JXADC with "LVDS_25 input/output" (with V_ADJ=2.5V). However, the discussion in has led to the result that LVDS-standard is not supported without changing the board. I would recommend to change the reference manual at this point. The documentation should clearly name supported standards especially if it is targeted to students that may not know all details of the IO-standards. The best way of a replacement of "LVDS" would be a list of IO-standards that work on this connector without changing the board. If the list is too long (the list of standards supported by Artix-7 fills several pages) it can be moved to the appendix. The minimal solution would be the replacement of "LVDS" by "differential" and let to the user/student to find out if a certain standard can be implemented with the board. Btw. There is a small typo in the table: The 3rd differential pair of JXADC is 3-9 (according to the schematic).
  5. Thanks a lot for your help! For me it looks like a weakness in the documentation of the board. "Differential" would be a better wording than "LVDS" which refers to a standard. Changing the board is a bad choice for me because I want to use the board in different student projects. In my project we changed to the FMC connector which provides many LVDS lanes that comply with the standard. This was not my first choice because the PCB layout becomes a little more complicated and the connector is a little more costly. Thanks again for the fruitfull discussion! Jens
  6. Many thanks for your comments! I'm also convinced that it works without the series resistors and the diodes. It is also clear that removing these elements from the board will void warranties. However, the "Nexys Video™ FPGA Board Reference Manual" (Revised May 30, 2017) describes in Table 9 (page 20) the "Recommended usage" of the pins in question with "LVDS_25 input/output". Does this mean that Digilent supports LVDS_25 for the board without any "illegal" modifications? Or is there an official support with limited performance as @jpeyron suggests? My limited technical understandig says that additional 2x100 ohm series resistors together with the ~4mA current of LVDS requires the LVDS outputs of the FPGA to provide additional 0.8V (to the 0.4V from the 100 ohm termination). It becomes even worse if two Nexys boards are coupled via Pmod and LVDS (additional 1.6V on output side than normal). I'm not sure if the Artix-7 can provide this relatively high differential voltage. Xilinx DS181 (v1.22) table 11 on page 10: V_ODIFF(max) = 600mV, V_IDIFF(min) = 100mV Jens
  7. Hello! I use Nexys Video board and plan to use a Pmod connector with LVDS standard (input and output). Following the reference manual, the only Pmod connector that provides LVDS (LVDS_25) for input and outputs is JXADC (with V_ADJ=2.5V). This connector is equipped with 100 ohm series resistors. The Xilinx documentation UG471 (v1.8, pages 91-93) does not describe that series resistors are recommended or required. Is it possible to use Pmod connector JXADC for LVDS inputs and outputs with that board? Or must I short cut the series resistors (R42-R45/R47-R50)? Many thanks in advance!