chcollin

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Everything posted by chcollin

  1. OK, I figured it out, I had to play with the mpd file to explicit input clock freq and clock factor, so that the output frequency could be calculated. However, this led me to another error : MPMC clock mem seems to be only PLL_ADV compatible ... so my DCM module didn't comply this specification. Due to the limited number of DCM and PLL on the Atlys board, I finaly decided to review the entire clock design. I ended up designing this : 1/ Removed the clock_generator_0 module as I didn't know if the module would generate clocks with DCM or PLL or both. 2/ Added a self made clock generator module. It takes at input system clock (100MHz), feeds a CLK_GEN (*9/40) (VCO 900MHz) into a DCM_SP (*11/10) (VCO 247.5MHz) to get one only output clock at 24.75MHz that fits quite well for my needs. 3/ Modified pll_module_0 : input is the 24.75MHz clock defined earlier, mult *30 and three output clocks: /10 to get 74.25MHz for pixel clock and system clock /5 to get pixel clock 2x /1 to get pixel clock 10x 4/ Added another PLL module : input is the 24.75MHz clock defined earlier, mult *23, div /1 to get 594MHz (8 times the system clock) to clock the MPMC Memory clock. This way, MPMC is clocked by a PLL and I have enough timing resources available on the Atlys to design this. However, I now am facing another problem !!! (yes...) It seems there is a constraint problem when generating bitstream. The error message is the following : ERROR:Place - ConstraintResolved NO placeable site for hdmi_out_0/hdmi_out_0/Inst_dvi_out_native/ioclk_buf ERROR:Place - ConstraintResolved NO placeable site for MCB_DDR2/MCB_DDR2/mpmc_core_0/gen_spartan6_mcb.gen_spartan6_bufpll_mcb.bufpll _0 ERROR:Place - SIO has over-constrained componet hdmi_out_0/hdmi_out_0/Inst_dvi_out_native/ioclk_buf to have to placeable sites. Constraints come from driver constraints AND load IO constraints I guess this is a constraint problem as I didn't had constraints regarding my "home made" clock generator nor the second PLL module... For those interested, you can find the clock generator source files and the system.ucf file attached to this post. If someone can help me solve this new problem, that would be very nice. Cheers ! system.ucf dcm_720p_v2_1_0.mpd dcm_720p.vhd
  2. OK, I've been working on this, unsuccessfully 😢 This is the design I've built : 1/ Clock generator : one single ouput : 22.5MHz from 100MHz internal clock (a single DCm x9/40 should achieve this but I might be generated somehow else) 2/ PLL module x33 / (1, 10, 5) to get 742.5MHz (pixel_clock_10x), 74.25MHz (pixel_clock + system_clock (PLB bus etc)), 148.50MHz (pixel_clock_2x) 3/ DCM master/slave module (master x11/10 [VCO 247.5MHz, output 24.75MHz], slave x24 /1 [VCO 594MHz, ouput 594MHz]), driving MPMC memory clock I thought this would go smooth but unfortunatly, I'm facing MPMC clock problems. First bitstream generation form XPS, I got an error telling me that C_MPMC_CLK_MEM_2X_PERIOD_PS could not be calculated and was out of range. After reading MPMC documentation (page 6) : Clock memory value is calculated automatically based on what is connected to Port MPMC_Clk_Mem_2x in XPS (for example a clock_generator output or a signal/port with MHS tag CLK_FREQ = xxxx.) The value can be overwritten; if set by the user, it is not calculated. So I decided to modify system.mhs to give C_MPMC_CLK_MEM_2X_PERIOD_PS the value 1684 ps (which is in the range given in the doc). This value is the period for a 594MHz clock. However, now I get the following error message : ERROR:EDK:4061 - INSTANCE: MCB_DDR2, PARAMETER: C_MPMC_CLK_MEM_2X_PERIOD_PS - Given value (1684) is incorrect. The expected value is 44444. Please update the value in MHS - /opt/Xilinx/Projects/HDMI_Rotator/project/system.mhs line 182 ERROR:EDK:3371 - Conversion to XML failed. make: *** [SDK/SDK_Export/hw/system.xml] Error 64 I don't know what to do with this error and where this 44444 value is taken from ! Can anybody help, please ?
  3. Hi @[email protected], Thank you for the interest you show regarding my project. To sum it up : This is a Spartan 6 PLB project with Microblaze. It reads video from hdmi_in and stores it in RAM (after image manipulation) thanks to a Multi Port Memory Controler (MPMC) / Video Frame Buffer Controler PIM (VFBC). RAM is then read by another VFBC that outputs (supposedly @720p, at least that's what I am trying to do now : getting a pure 720p signal, specs compliant) through hdmi_out module. It is the MPMC that needs this 600MHz clock for internal use. From what I have understood, it is supposed to run at 8 times the frequency of the Microblaze. Clock generator delivers a 75MHz clock for the Microblaze and a 600MHz clock for the MPMC. As you may have read earlier, I've haded a 22.5MHz clock to the clock generator that feeds a PLL Module to get 74.25MHz at output (720p spec compliant frequency). Of course, the easiest thing would be to set clock generator to output a 74.25MHz for the Microblaze and a 594MHz clock for the MPMC... But Spartan 6 cannot do that (at least Atlys can't). Now I was wondering : Would it be possible to use clock generator to output a 22.5MHz clock into a PLL module to get my 74.25MHz clock and then use this clock signal as a clock-in to another PLL module that would generate all clocks for the system ? (x8/8 for the Microblaze and hdmi_out, x8/1 for the MPMC ...). I really don't know if this would not interfere with all other components of the system -PLB bus etc)... I might try that.
  4. Thank you @[email protected], The problem was not as difficult as I thought, as we say in french : the problem mostly resides between the seat and the keyboard The fact that I am not in the eletronics nor the FPGA thing makes it sometimes difficult to me to understand how things work. I finaly endend up adding another clock to the clock generator and modified PLL module configuration. Reference clock is 100MHz and clock wizard allowed me to add a 22.5MHz clock to the system. This 22.5MHz clock feeds a PLL module with multiply factor set to 33, which gives me exactly 742.5MHz. The PLL module outputs 3 clocks : CLK0 with divide factor set to 1 for pxlclk_x10 CLK1 with divide factor set to 10 for pxlclk (74.25MHz, 720p specs freq) CLK2 with divide factor set to 5 for pxlclk_x2 Here is a screenshot of the internal clock schematics : Bitstream generation fails if I do not deselect "Treat timing closure failure as an error" in Project Options. A close look using Time Analyzer shows this : ================================================================================ Timing constraint: TS_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT2 = PERIOD TIMEGRP "clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT2" TS_sys_clk_pin * 0.75 HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 498357 paths analyzed, 31206 endpoints analyzed, 10 failing endpoints 10 timing errors detected. (10 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 734.895ns. -------------------------------------------------------------------------------- Slack (setup path): -7.306ns (requirement - (data path - clock path skew + uncertainty)) Source: hdmi_out_0/hdmi_out_0/vfbc_rd_reset_i (FF) Destination: MCB_DDR2/MCB_DDR2/VFBC2_INST.vfbc/VFBC1_PIM_NGC/UVFBC/rdfifo_reset_dly1_0 (FF) Requirement: 0.135ns Data Path Delay: 1.405ns (Levels of Logic = 1)(Component delays alone exceeds constraint) Clock Path Skew: -5.487ns (4.455 - 9.942) Source Clock: hdmi_out_0_VFBC_OUT_cmd_clk rising at 1319.865ns Destination Clock: clk_75_0000MHzPLL0 rising at 1320.000ns Clock Uncertainty: 0.549ns Clock Uncertainty: 0.549ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.472ns Phase Error (PE): 0.310ns Maximum Data Path at Slow Process Corner: hdmi_out_0/hdmi_out_0/vfbc_rd_reset_i to MCB_DDR2/MCB_DDR2/VFBC2_INST.vfbc/VFBC1_PIM_NGC/UVFBC/rdfifo_reset_dly1_0 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X30Y100.BQ Tcko 0.525 hdmi_out_0_VFBC_OUT_rd_reset hdmi_out_0/hdmi_out_0/vfbc_rd_reset_i SLICE_X31Y99.C4 net (fanout=1) 0.507 hdmi_out_0_VFBC_OUT_rd_reset SLICE_X31Y99.CLK Tas 0.373 MCB_DDR2/MCB_DDR2/VFBC2_INST.vfbc/VFBC1_PIM_NGC/UVFBC/rdfifo_reset_dly1<0> MCB_DDR2/MCB_DDR2/VFBC2_INST.vfbc/VFBC1_PIM_NGC/RdDataPortIn[0]_MReset_n1_INV_0 MCB_DDR2/MCB_DDR2/VFBC2_INST.vfbc/VFBC1_PIM_NGC/UVFBC/rdfifo_reset_dly1_0 ------------------------------------------------- --------------------------- Total 1.405ns (0.898ns logic, 0.507ns route) (63.9% logic, 36.1% route) I guess this is due to the fact hdmi_out clock (now at 74.25MHz) does not align with MPMC clock frequency (600MHz). I don't know if this really matters... It probably does but I don't know how to solve this. Anyway, if I deselect the option about timing closure failure, I can generate a bitstream and try it. The project runs. Now if I connect the Atlys to a TV, things run smooth. However, if I connect it to a less tolerant device (such as PC LCD monitor), here is what I get : Video information now tells me video is [email protected] (formerly it stated [email protected]) : that's better I notice slight horizontal shaking. Supposedly, the video signal has a pixelclock @74.25MHz, total pixel per frames 1650x750 (h/v front porch, back porch and sync follow the specs). Does anybody have any hint on why this horizontal shaking (slight but present) ? I have a Marseille mCable HDMI cable (anti aliasing / upscaler 720p/1080p, many video corrections I wish to use on Atlys output). This device seems very strict on input signal and does not accept my generated signal as input. Obviously there is still something wrong with the TMDS signal generated though output frequency is now specs compliant. I'd really appreciate if you could give me hints on completing this issue. Cheers
  5. OK, for the 74.25 MHz problem, I think I am going to use a custom DCM core, with clock input @100 MHz Master DCM will do x11/16 Slave DCM will do x27/25 This should give me exactly 74.25 MHz as output.
  6. Question 2 posted in orginal message
  7. Got my answer : "Unfortunately the Atlys is unable to handle 1080p60Hz because of the timing requirements of its FPGA. This is not something that can be changed via an update. The reason the Atlys can't handle a 1080p60Hz signal is because it requires deserialization/serialization at a rate of well over 1 Gb/s, and the Atlys can only handle deserialization/serialization at a max of 950 Mb/s." Is-1080p60-video-possible-at-all-with-a-Spartan-6-board-Atlys
  8. Hi folks, I truely doubt it but can you confirm Atlys cannot output [email protected] on its HDMI port ? Thx
  9. OK, final post and probably most humorous... I thought I had no choice but to use a bootloader to launch apps from flash... which if true is your app is too big to fit in BRAM. In that case, you need a bootloader to copy app to DDR where it can fit and start. This is the bootloader's sole purpose ! I never realized that I didn't need a bootloader if my app was small enough to fit in BRAM, which is the case (Atlys has 2.1Mb of them) So I ended up giving up this bootloader thing... Sorry for having made you very kind guys at Digilent waste your time ! 😢 Especially a big thank you @JColvin who helped me much on this thing even though I finally found a workaround (or should I say a straightforward method, the bootloader being the workaround !) Cheers
  10. For information, here are some return codes I get when bootloader runs : XSpi_Initialize RC: 0 XSpi_Start RC: 0 XIsf_Initialize RC: 1 I think the latter indicates an error...
  11. Update 3 - Major step in progression ! I finally ended up programming the SPI Flash First, the bootloader would not work. It was due to a bad value for XPAR_SPI_FLASH_DEVICE_ID. Looking at bootloader.c, I noticed this comment : /* * Initialize the SPI driver so that it's ready to use, * specify the device ID that is generated in xparameters.h. */ SO I checked SREC_bsp/microblaze_0/include/xparameters.h | grep SPI and found this declaration : #define XPAR_XPS_SPI_0_DEVICE_ID 0 #define XPAR_SPI_0_DEVICE_ID 0 And finaly declared in bootloader.c : #define SPI_DEVICE_ID XPAR_SPI_0_DEVICE_ID After recompiling and programming flash, the bootloader now outputs messages. However, there seems to be a problem with finding srec image, as the bootloader raises an error : SREC Bootloader Loading SREC image from flash @ address: 00170000 ERROR: Error while reading an SREC line from flash After a few reading, I'm a bit confused and have several questions : 1) Should FLASH_IMAGE_BASEADDR in blconfig.h be an absolute address or relative one ? I've seen some users telling it should be flash base address + offset. In lscript.ld, I can see : ilmb_cntlr_dlmb_cntlr 0x00000050 So I tried setting FLASH_IMAGE_BASEADDR to 0x00170050 but same result (didn't change off set MCS generation, kept using 0x00170000) 2) Shouldn't the SREC image be modified with the bootgen command ? Once again, I've read users with similar bootloader error talking about this command. I'm getting close to it, but it's not done yet ! Anyone with a suggestion ? That would be much appreciated. EDIT : There seems to be a problem for the bootloader programm to access the SPI Flash. I've been printing data retrieved by srec read function in bootloader.c and it displays only 0s. So there might be a problem with serial flash family and/or interface. I'm gonna try different values and see if I get better results. Cheers
  12. OK, linker doesn't find xilisf functions. There might be problems with missing -L or -l options to gcc, but this is an ISE issue, so I'll post on xilinx forum instead. I'll be back after I solve this problem and try to boot The Atlys with this thing EDIT : For some unknown reason, the "Generate Linker Script" Option generates a objects.mk file with missing -xilisf option for linker. I ended up editing this file manually to add this option and finally every thing went smooth. I now have a download.bit ready to be uploaded to Atlys' SPI Flash Chances are low that everything works ok at first try, but it's going in the right direction ! Thx again for your help @JColvin
  13. Thx @JColvin I'll let you know soon how things evolved
  14. @JColvin , first off, many thanks. It's very kind of you having done all this research and giving me all those tips. I really appreciate it. Now, about the XPAR_SPI_FLASH_DEVICE_ID thing : I(ve been downloading ISE 12.4 and searched header files for this symbol ... unsuccessufully. I'm starting to think there is a missing header file / declaration with the tutorial. But all your tips might help me on this trial. I've been greping xilisf header files about N25Q128, and this is what I found in xilisf_intelstm.h : #define XISF_NM_DEV_N25Q128 0xBA18 /**< Device ID for N25Q128 */ #define XISF_MIC_DEV_N25Q128 0xBB18 /**< Device ID for N25Q128 */ So... maybe the STM flash family is the good choice and maybe I should declare #define XPAR_SPI_FLASH_DEVICE_ID XISF_NM_DEV_N25Q128 ... assuming MIC is Micron and NM is Numonyx ... OK, it"s a bit straight forward, I admit... But it might be worse trying this. I'll try programming SPI Flash with this parameter value and see how things go. Cheers
  15. Update 2 OK, the bootloader side of things happens to be the dark side of things People here at Digilent might help me on one point (googleing didn't give results). Could anyone tell me what is the flash family I should choose for the xilisf library ? Here is what is available : #define ATMEL 1 /**< Atmel family device */ #define INTEL 2 /**< Intel family device */ #define STM 3 /**< STM family device */ #define WINBOND 4 /**< Winbond family device */ #define SPANSION 5 /**< Spansion family device */ #define SST 6 /**< SST family device */ Secondly : Following the tutorial given by @JColvin, it is suggested to replace bootloader.c with a custom one (it substitutes regular memory reads by SPI Flash reads). I managed to find this custom bootloader.c file (attached to this post), unfortunately it doesn't compile. preprocessor rises an error for undeclared symbol XPAR_SPI_FLASH_DEVICE_ID. I've been greping all header files in ISE 14.7 for that symbol... unsuccessfully 😢 Any suggestion ? Cheers bootloader.c
  16. Update 1 I managed to add xps_spi core to HDMI_DEMO project and export design 😀 As I didn't know how to configure it, I started a new XPS project from scratch using BSB wizard and Atlys_PLB_BSB_Support files to retrieve those needed information. Then, back to HDMI_DEMO project, I configured my new xps_spi core as follows : Added those lines to system.ucf : Net xps_spi_0_SCK_pin LOC=R15 | IOSTANDARD=LVCMOS33; Net xps_spi_0_MISO_pin LOC=R13 | IOSTANDARD=LVCMOS33; Net xps_spi_0_MOSI_pin LOC=T13 | IOSTANDARD=LVCMOS33; Connected xps_spi core ports to those. Finaly, configured xps_spi core as indicated in screenshots. Export was successful. I'll do the SDK part tomorrow. Thanks again @JColvin
  17. Wow ! Many thanks @JColvin ! This solution seems very promising. I'll try this asap and will tell you if this solves my problem. I'm almost sure it will as it depicts exactly what i'm looking for. At least it should be a milestone on the path to victory. Cheers
  18. Actually, I'd like to find answers to the questions asked in this thread : https://forums.xilinx.com/t5/Embedded-Development-Tools/Possible-to-use-a-SPI-SREC-Bootloader-on-a-plb-based-microblaze/td-p/690251
  19. Thank you @Cristian.Fatu, however I'm afraid this is not "that simple"... From what I have understood, the tricky part is to generate a .bit file that contains both EDK implementation AND SDK PLB Microblaze binaries as well as a bootstrap loader. If this solution is documented over the web for AXI based projects, I can't find any piece of info about PLB based projects. Once this .bit file is obtained, indeed the way to store it is as you mentionned (using Adept). As you might have understood now, my problem is not to store data to SPI, but to generate a bootloadable .bit file containing both EDK implementation and SDK LPB Microblaze binaries. Hope this can be done ... Cheers
  20. Hi FPGA gurus ! Merry Christmas and happy new year to all of you FPGA lovers at Digilent ! I'm trying (unsuccessfully) to store Atlys HDMI demo to SPI/Flash so that whenever I turn the Atlys board on the project runs, without the need to upload and launch it through SDK. Atlys HDMI demo is a PLB based project and the only piece of info I can find about storing projects to SPI/Flash is for AXI based projects. Can anybody help me achieving this ? Any help would be greatly appreciated. Cheers
  21. This solution seems to be suitable for AXI-based projects... whereas I'm using PLB 😢 That's sad...
  22. I might answer partially my own question as I have found this tutorial : How To Store Your SDK Project in SPI Flash It is for Vivado but with a little luck, this might work for ISE 14.7 too. I'll post some time soon to tell you if I managed to have it work or if I need help !
  23. Thank you @[email protected], I'll have a look at your project when I have time. However, it was not my intention to rewrite the xps_iic EDID module, as I'm totally satisfied with what I have now. I'm just trying to understand how to store the whole project to Atlys' SPI/FLASH so that whenever I turn it on the project runs, without the need to launch it through SDK. Cheers
  24. I have no hint as to why this was designed this way. All I can say is that Microblaze handles IIC interrupts for feeding HDMI connector with supported resolution infos. Quoting the demo documentation : "Implementing an EDID transmitter so that attached devices will recognize the Atlys as a display device Input sources that require EDID packets to recognize a device must be attached after the software has been loaded to the FPGA. This is because the IIC controller must be configured properly in order to respond to the EDID requests which occur just as the device is plugged in.  The transmitted EDID packet may be altered in the hdmi_demo.h header file." I guess this was, at that time (2013), the way to use HDMI in connector. In header file : /* * EDID array definition. Changing these values changes the EDID * packet that is sent over the E-DDC wires. It contains information on which * resolutions the device supports. Currently, this packet provides fairly * generic resolution support. Note that using resolutions with widths larger * than the line stride of the hdmi_output core results in a choppy picture. */ In source code : /*** IicHandler ** ** Parameters: ** CallBackRef - Pointer to NULL ** ** Return Value: ** None ** ** Errors: ** None ** ** Description: ** This function is connected to the interrupt handler such that it is ** called whenever an interrupt is triggered by the IIC core. It is ** designed to behave like a monitor on an E-DDC interface. It outputs ** the data held in rgbEdid as its EDID. */
  25. Hi FPGA gurus ! This might be my forever last question :D My project is complete, all bugs and customizations done. I wanted to get rid of the microblaze part but I realized I couldn't since HDMI In connector needs xps_iic and microblaze for the EDID thing. So, here is my question, as I didn't find any answer to it : How can I store the whole project into Atlys so that I don't need to download and run it from SDK every time ? Especially, the C program needs to be run on bootup so that EDID interrupts are handled. To resume : What's the process so that whenever I turn the Atlys on, my implementation and program run ? Can anybody help on this ? After 2 years I'm finally seeing the light at the end of the tunnel !! Many many thanks in advance. Cheers