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  1. OK OK, forget about it, I was messing too much with mhs file .... Finaly I could connect hdmi_in and hdmi_out modules. Now Let me synchronize both writing and reading ....
  2. I finaly managed to connect both ports between hdmi_in and hdmi_out modules, at least i believe I did as shown in the screenshot below. However, I get mapping errors : ERROR:MapLib:979 - LUT6 symbol "hdmi_out_0/hdmi_out_0/vfbc_cmd_data_i_13_rstpot" (output signal=hdmi_out_0/hdmi_out_0/vfbc_cmd_data_i_13_rstpot) has input signal "hdmi_in_0_FB_SELECT" which will be trimmed. See Section 5 of the Map Report File for details about why the input signal will become undriven. WARNING:MapLib:701 - Signal hdmi_in_0_SW_pin<1> connected to top level port hdmi_in_0_SW_pin<1> has been removed. ERROR:MapLib:978 - LUT6 symbol "hdmi_out_0/hdmi_out_0/vfbc_cmd_data_i_13_rstpot" (output signal=hdmi_out_0/hdmi_out_0/vfbc_cmd_data_i_13_rstpot) has an equation that uses input pin I0, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). This is depressing 😢
  3. Thank you @jpeyron, I hope they'll find a solution Attached to this message, some project files related to ports and a screen shot to show you what i did concerning bus interfaces (creation of directed bus FBSB). Also, on picture hdmi_in.png, i don't understand why port FB_SELECT is named FBSB.{ FBSB.FB_SELECT} whereas I was expecting some expandable button like SPLB and VFBC_OUT (I just tryed to do exactly as it was done for VFBC_OUT... without success) confiles.tar
  4. OK guys, I might not be completly out of trouble There is some sort of tearing due to the fact that hdmi_out module reads from the frame buffer while it is being written. To correct this, I had the idea to use two frame buffers : while hdmi_in module writes vertical stripes to the first frame buffer, hdmi_out would read from the other untouched frame buffer. Then invert frame buffers. To do this, I wanted to share a simple signal (std_logic) between hdmi_in module and hdmi_out module to describe which frame buffer to use... The problem is I don't have a single idea on how to do this as I really am not comfortable with all the MHS, MPD, UCF files .... I "managed" to connect both modules with a custom bus ... which i'm not sure is the good thing to do. But I don't know how I can connect ports. I've been trying all day long and feel a bit lost. I'm sure it's very easy for people comfortable with FPGA, so I would really appreciate a little help. If you need any files from my project, don't hesitate to ask. Please, if someone can help ... Cheers
  5. I finaly made it !!!! As previously teased, here is a video of the resulting process : Many thanks @jpeyron and @sbobrowicz for their help, it was quite challenging to me as this FPGA thing was totally new to me. Cheers
  6. Just to keep you informed, the "double pixel" hack works. Now i'm debugging the bram buffer thing. Hope to post a first video soon ?...
  7. Many thx @jpeyron Nevermind, I think I have found some turnaround that I might soon try. In hdmi_out, I do not need to read the entire frame buffer as most on the screen is blackend except for the rotated 480x640 image (in reality 960x640 since pixel are doubled at write time). Since i'm only going to use the right half of the 1280x720 screen (left half is blakend), I'm going to use another BRAM to store the current line at pxlclk rate. While storing it i'll be sending black pixels at dvi_encoder until I reach the middle of the line and then whith dual port BRAM i'll start sending for pixels previously stored in BRAM while keeping storing remaining line pixels and so forth until the end of the line. That should bring me the solution to my problem. I'll keep you informed. Cheers
  8. After almost one year inactive, i'm trying to play with this HDMI demo again My goal is to use it as a basis for 90° rotating a 480p video source and display it on a 720p display. To achieve this, i'm using 18K BRAMs to store lines and then read columns from the BRAMs to the VFBC writer as lines. As there is only 2.1 Mb of BRAMs on the Atlys, I cannot store the entire frame in BRAMs (2.1 Mbits / 18Kbits = 120 BRAMs while having 480 lines to store) Also, there are VFBC X Size and Stride alignement constraint : A minimum of 128 bytes must be writen which means that I need 64 BRAMs minimum (64 x 16 bits = 128 bytes). Then, my first idea was to store 64 lines from the dvi_decoder to a first set of 64 BRAMs, while reading another set of 64 BRAMs and writing them to VFBC as a (64 x 640 x 16) column, and then interverting BRAM sets (write 64 lines form dvi_decoder to BRAM set A while writing 64 columns form BRAM set B to VFBC, then write 64 lines form dvi_decoder to BRAM set B while writing 64 columns form BRAM set A to VFBC, then write 64 lines form dvi_decoder to BRAM set A while writing 64 columns form BRAM set B to VFBC and so forth ...) The problem is that there aren't 128 available BRAMs on the Atlys. So I thought that instead of using 2 sets of 64 BRAMs, I could use 2 sets of 32 BRAMs and use a simple trick to bypass the VFBC 128 byte alignement constraint : padding 16 bit pixel data with 16 0's, so that the X size would be 32 pixel * 32 bits = 128 bytes. The problem is that I couldn't set up MPMC to use 32 bit words instead of 16 bit words. It seems the DDR2 RAM on the Atlys does not allow this. So this is my first question : Did I do something wrong or is it possible to set up MPMC / VFBC on Atlys so that reads and writes are 32-bit word long ? As I couldn't set MPMC correctly to 32 bits, I had a hack idea : I'll keep using 2 sets of 32 BRAMs, storing frame lines as 16 bit words, but when writing to VFBC, I'll set X size to 128 and use a pixel clock x2, duplicating each pixel in the frame buffer. It was a trick to write a 32 columns of 16-bit wide pixel meanwhile the 128 alignement constraint. The idea was to do the same trick in the hdmi_out module : read data from frame buffer at twice pixel clock and write to dvi_coder at pixel clock dropping half of the pixels (I.e dropping the duplicated pixels). Unfortunatly, this does not work either !!! (this is very sad as I was proud of this trick ) The data in the frame buffer is correct : If I set VFBC_RD_CLK at pxlclk (720p = 75 MHz), then I can see all pixels duplicated and image is twice as larger. However, when I set VFBC_RD_CLK to pxlclk_x2 (150 Mhz), It seems the VFBC PIM doesn't work. So this is my second question : Is it possible with Atlys to read from VFBC at 150 MHz ? There are things that I have read in DS643 ( LogiCORE IP Multi-Port Memory Controller (MPMC) (v6.03.a) ) page 184, that I dont quite understand : First off, there seems to have frequency limitations but those for Spartan 6 are not given... Secondly, what is this thing about timing constraints ? To quote : "VFBC Timing Constraints MPMC provides a Tcl script that generates the timing constraints within a UCF file automatically for the VFBC PIM. For the timing constraints to be set correctly, the clock frequency of MPMC_Clk0 must be specified in the MHS file. The MHS file must have the CLK_FREQ value set for all input clock ports. The following code snippet is an example of an MHS file PORT declaration showing the direction as Input (I) and the CLK_FREQ set: PORT display_clk_pin = display_clk, DIR = I, SIGIS = CLK, CLK_FREQ = 27000000, BUFFER_TYPE = IBUFG If the clock frequency is not set, the automatically generated VFBC timing constraints will assume the frequencies listed in Table 90, page 184 for the given device family" Does that have a relation with the problems I am facing ? Thanx a lot to any soul who will help my with this. Cheers and Happy New year
  9. Hi @jpeyron Thanks a lot for the link. Whatever I tried, I never managed to solve the problem. I finally ended up setting a new linux native partition on which I installed Centos 6.9. It's been a very hard time making Xilinx EDK work flawlessly (I had to install i686 libs, update cairo libs, recompile usb cable drivers, change serial port access libs ...), but I finally have a fully working ISE 14.7 setup, no SDK crashes, JTAG and UART via USB working Happy !
  10. Hi FPGA gurus ! I am facing trouble while trying to attach my Atlys USB JTAG device to a Centos 6 virtualbox VM. I recently had no choice but to upgrade my computer from Windows 7 to Windows 10. As a Windows 10 version of ISE 14.7 was available, I decided I could do the upgrade before realizing that ISE 14.7 for Windows 10 was indeed ISE 14.7 for Linux running a VirtualBox... Nevermind. The problem is that it seems I can't attach Digilent USB JTAG to the VirtualBox. Here is my configuration : Windows 10 Pro VirtualBox 5.2.8 (I upgraded it so that I could install Extensions to enable USB 2 and USB 3 support) Adept2 is installed on Windows 10 and works fine, Atlys board is recognized and I can run the test application OK. Now, here is my problem : Let's turn on the computer first and do a fresh test ! Atlys Board is attached to USB ports (JTAG and UART) but is turned off. VirtualBox USB configuration is configured as shown in USB_parameters.jpg Now, let's turn VM on, Atlys board still off. The attachable USB device list in VB is shown in USB_devices_atlys_off.jpg As you can see, neither JTAG nor UART devices are listed, which is expected as Atlys board is off. Now, let's turn the Atlys board on and see if the listing has changed... It has ! as shown in USB_devices_atlys_on_1.jpg Also, you can see in Device_mgr.jpg that Windows has no driver problem with JTAG and UART devices. You may notice UART device is automatically attached. Looking at /dev/tty* shows that the UART device is now available through /dev/ttyACM0 as shown in TTY_devices.jpg Let's have a look at the JTAG device status (USB_devices_atlys_on_2.jpg), it reads "captured", whatever that means ... Now, let's try attaching it... It raises an error with message shown in Digilent_USB_JTAG_attachment_error.jpg "USB device is busy with a previous request" :/ This is sad ... Of course, no other device appears in /dev/tty* Greping dmesg for FTDI pattern returns Nothing. Only UART USB devices appears in dmesg log... I've tried the same test with USB 3 (xHCI) configuration selected. Do any of you have an idea on how I could attach the USB Digilent JTAG device to my Centos 6 VirtualBox machine ? Any help will be highly appreciated. Thanx a lot. Cheers
  11. Thank you @jpeyron, I'll have a look at the VmodCam example, it should bring me some good start. Cheers
  12. Hi, Does anyone know if/where I can find an AXI4 example running on Atlys similar in functionnality to the HDMI PLB demo ? The example would show how to read frames from HDMI in, store to memory via AXI4 VDMA core, and read from memory to HDMI out. Thanx !
  13. Thank you so much @sbobrowicz ! I've been away from my project and this forum for a while. Your explanation makes it so clear now. Thank you very much and happy new year. Cheers
  14. Thx @jpeyron, i'm going to ask Xilinx as you advice. I'll post back here if I ever get any answer from Xilinx. Cheers
  15. Hi everyone, I've been reading Xilinx's DS643 pdf on MPMC configuration (v6.06.a). Table 91 page 170 lists the maximum frequency that can be used for the VFBC interface clocks, VFBC_Cmd_Clk, VFBC_Wd_Clk and VFBC_Rd_Clk. Only Spartan-3A DSP, Virtex-4 and Virtex-5 devices are listed. Where can I find the maximum frequency that can be used to clock VFBC on Atlys spartan-6 ? Thanx a lot, cheers.