chcollin

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  1. OK, I figured it out, I had to play with the mpd file to explicit input clock freq and clock factor, so that the output frequency could be calculated. However, this led me to another error : MPMC clock mem seems to be only PLL_ADV compatible ... so my DCM module didn't comply this specification. Due to the limited number of DCM and PLL on the Atlys board, I finaly decided to review the entire clock design. I ended up designing this : 1/ Removed the clock_generator_0 module as I didn't know if the module would generate clocks with DCM or PLL or both. 2/ Added a self made clock g
  2. OK, I've been working on this, unsuccessfully 😢 This is the design I've built : 1/ Clock generator : one single ouput : 22.5MHz from 100MHz internal clock (a single DCm x9/40 should achieve this but I might be generated somehow else) 2/ PLL module x33 / (1, 10, 5) to get 742.5MHz (pixel_clock_10x), 74.25MHz (pixel_clock + system_clock (PLB bus etc)), 148.50MHz (pixel_clock_2x) 3/ DCM master/slave module (master x11/10 [VCO 247.5MHz, output 24.75MHz], slave x24 /1 [VCO 594MHz, ouput 594MHz]), driving MPMC memory clock I thought this would go smooth but unfortunatly, I'm
  3. Hi @[email protected], Thank you for the interest you show regarding my project. To sum it up : This is a Spartan 6 PLB project with Microblaze. It reads video from hdmi_in and stores it in RAM (after image manipulation) thanks to a Multi Port Memory Controler (MPMC) / Video Frame Buffer Controler PIM (VFBC). RAM is then read by another VFBC that outputs (supposedly @720p, at least that's what I am trying to do now : getting a pure 720p signal, specs compliant) through hdmi_out module. It is the MPMC that needs this 600MHz clock for internal use. From what I have understood, it is sup
  4. Thank you @[email protected], The problem was not as difficult as I thought, as we say in french : the problem mostly resides between the seat and the keyboard The fact that I am not in the eletronics nor the FPGA thing makes it sometimes difficult to me to understand how things work. I finaly endend up adding another clock to the clock generator and modified PLL module configuration. Reference clock is 100MHz and clock wizard allowed me to add a 22.5MHz clock to the system. This 22.5MHz clock feeds a PLL module with multiply factor set to 33, which gives me exactly 742.5MHz. The PLL mod
  5. OK, for the 74.25 MHz problem, I think I am going to use a custom DCM core, with clock input @100 MHz Master DCM will do x11/16 Slave DCM will do x27/25 This should give me exactly 74.25 MHz as output.
  6. Question 2 posted in orginal message
  7. Got my answer : "Unfortunately the Atlys is unable to handle 1080p60Hz because of the timing requirements of its FPGA. This is not something that can be changed via an update. The reason the Atlys can't handle a 1080p60Hz signal is because it requires deserialization/serialization at a rate of well over 1 Gb/s, and the Atlys can only handle deserialization/serialization at a max of 950 Mb/s." Is-1080p60-video-possible-at-all-with-a-Spartan-6-board-Atlys
  8. Hi folks, I truely doubt it but can you confirm Atlys cannot output [email protected] on its HDMI port ? Thx
  9. OK, final post and probably most humorous... I thought I had no choice but to use a bootloader to launch apps from flash... which if true is your app is too big to fit in BRAM. In that case, you need a bootloader to copy app to DDR where it can fit and start. This is the bootloader's sole purpose ! I never realized that I didn't need a bootloader if my app was small enough to fit in BRAM, which is the case (Atlys has 2.1Mb of them) So I ended up giving up this bootloader thing... Sorry for having made you very kind guys at Digilent waste your time ! 😢 Especially a bi
  10. For information, here are some return codes I get when bootloader runs : XSpi_Initialize RC: 0 XSpi_Start RC: 0 XIsf_Initialize RC: 1 I think the latter indicates an error...
  11. Update 3 - Major step in progression ! I finally ended up programming the SPI Flash First, the bootloader would not work. It was due to a bad value for XPAR_SPI_FLASH_DEVICE_ID. Looking at bootloader.c, I noticed this comment : /* * Initialize the SPI driver so that it's ready to use, * specify the device ID that is generated in xparameters.h. */ SO I checked SREC_bsp/microblaze_0/include/xparameters.h | grep SPI and found this declaration : #define XPAR_XPS_SPI_0_DEVICE_ID 0 #define XPAR_SPI_0_DEVICE_ID 0 And finaly decla
  12. OK, linker doesn't find xilisf functions. There might be problems with missing -L or -l options to gcc, but this is an ISE issue, so I'll post on xilinx forum instead. I'll be back after I solve this problem and try to boot The Atlys with this thing EDIT : For some unknown reason, the "Generate Linker Script" Option generates a objects.mk file with missing -xilisf option for linker. I ended up editing this file manually to add this option and finally every thing went smooth. I now have a download.bit ready to be uploaded to Atlys' SPI Flash Chances are low that ever
  13. Thx @JColvin I'll let you know soon how things evolved
  14. @JColvin , first off, many thanks. It's very kind of you having done all this research and giving me all those tips. I really appreciate it. Now, about the XPAR_SPI_FLASH_DEVICE_ID thing : I(ve been downloading ISE 12.4 and searched header files for this symbol ... unsuccessufully. I'm starting to think there is a missing header file / declaration with the tutorial. But all your tips might help me on this trial. I've been greping xilisf header files about N25Q128, and this is what I found in xilisf_intelstm.h : #define XISF_NM_DEV_N25Q128 0xBA18 /**< Device ID
  15. Update 2 OK, the bootloader side of things happens to be the dark side of things People here at Digilent might help me on one point (googleing didn't give results). Could anyone tell me what is the flash family I should choose for the xilisf library ? Here is what is available : #define ATMEL 1 /**< Atmel family device */ #define INTEL 2 /**< Intel family device */ #define STM 3 /**< STM family device */ #define WINBOND 4 /**< Winbond family device */ #define SPANSION 5 /**< Spansion family device */ #de