chcollin

Members
  • Content Count

    71
  • Joined

  • Last visited

About chcollin

  • Rank
    Frequent Visitor

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. That was not the problem. Everything was due to VGA timings. Case closed.
  2. Hi, I am facing a strange issue with HDMI output on Atlys J2 connector, hope someone will help me understand. J2 outputs a 720p signal @74.25MHz, based on a modified version of HDMI Demo hdmi_out (I'm using an external clock instead of the 75MHz one in the demo). Everything goes smooth with any casual hdmi cable. However I own an active HDMI cable, from Marseille Inc. This active HDMI cable (called mCable) is a 1080p upscaler with anti-aliasing and sharpening processor. Unfortunately, when using this cable I get no signal on my TV set. I wrote to Marseille Inc support, her
  3. BTW, now J1 works fine, I managed to clock the whole system at 74.25 MHz ! It's been a long way, but finally made it !!! Thanx @zygotfor all the help you gave and explanations, that helped me much in the understanding of my problem.
  4. Solution posted here
  5. OK, I finally managed to have J1 working following this document. For archiving purpose, here's a picture of how jumpers should be set for using J1. N.B : Although not documented in Atlys datasheet, JP5 MUST BE LOADED to enable J1. Also, be careful with "J2", labelled SDA/SCL. Jumper must be set "horizontally".
  6. Thank you @zygot for all this explanations, that's very kind of you. I guess you are talking about JP12 jumper to select Vccio for IO bank 2. Lately, I've been working on acquiring hdmi signal on J1, but still unsuccessfully. As reported on this topic, i've been coding a core to act as an EDID emulator. This core is simply a PLB master core. At initialization, it configures xps_iic PLB slave IP cores as a DDC slave (address 0x50) and then catches interrupts from xps_iic to write EDID information to the xps_iic registers that handles DDC/I2C protocol with the host. Things work fin
  7. Also, generating bitstream raises an error with projects using HDMI J1 and J3 as inputs and J2 as output : Incompatible IOB's are locked to the same bank 0 Conflicting IO Standards are: IO Standard 1: Name = TMDS_33, VREF = NR, VCCO = 3.30, TERM = NONE, DIR = OUTPUT, DRIVE_STR = NR List of locked IOB's: hdmi_out_0_TMDS_pin<0> hdmi_out_0_TMDS_pin<1> hdmi_out_0_TMDS_pin<2> hdmi_out_0_TMDS_pin<3> hdmi_out_0_TMDSB_pin<0> hdmi_out_0_TMDSB_pin<1> hdmi_out_0_TMDSB_pin<2> hdmi_out_0_TMDSB_pin<3> IO Stan
  8. Hi, I've written a simple vhdl core to act as an EDID emulator. It's basically a PLB Master core, catching interrupts from a PLB Slave XPS_IIC core attached to HDMI SDA/SCL line to manage I2C/DDC protocole. This core works fine when xps_iic is connected to J3:IN I2C ports (M16 for SCL, M18 for SDA). However, nothing happens when the xps_iic is connected to J1:IN I2C ports (C13 for SCL, A13 for SDA). I guess I'm missing something with JP2 and JP4 jumpers. Can you please tell me the correct jumper settings to have J1:IN hdmi port act the same way as J3:IN ? Please note tha
  9. A last question @zygot, please. In case I could not find some clock generator board to clock my atlys, and knowing that the HDMI D plug shares pins with the pmod plug, especially clock pins, what do you think of this : Could I use some video device (for instance, some raspberry pi that I own), configured to display @720p and plugged into Atlys HDMI D port ? Would this, in your opinion, provide a decent 74.25MHz system clock for my scheme ? EDIT : I don't even know why bother use JA Type D HDMI plug, I could simply plug the raspberry into J3 Type A HDMI connector to get clock s
  10. Thank you very much @zygot for the time you spent on replying me, that's very nice of you. Unfortunately, I'm afraid your solution is the way to go... I say "unfortunately" because designing and making such a board is totally out of my field of skills ! Indeed, I am not into electronics at all, neither in the fpga thing as you might have understood from my naive questionnings :) Let me try to find someone able to do this for me, I hope I'll find. Once again, thank you very for all your replies, that led me to a clearer comprehension of my problem. Cheers.
  11. Thank you very much @zygot, your help is really appreciated. If some personnel at Digilent reading this thread could give me advice or point me to such a piece of hardware, that would be fantastic ! To sum it up, I need a 74.25MHz external clock device compatible with Atlys, ideally VHDCI plugable, right ?
  12. Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ |clock_generator_720p | | | | | | | _0_CLKOUT | BUFGMUX_X2Y2| No | 2175 | 0.682 | 2.391 | +---------------------+--------------+------+------+------------+-------------+ |hdmi_out_0
  13. Hi @zygot, Thank your for your reply 👍 I've read several times that cascading 2 DCMs is not advised by Xilinx, yet I wanted to give it a try... The thing is I wanted to remain in one sole CMT as Atlys only has 4 of those ... so I couldnt figure out any other way to achieve my frequencies. Clock wizard doesn't know about cascading DCMs, it only provides PLL and/or DCM, eventually cascaded (DCM2PLL or PLL2DCM). I've tried using the clock wizard, but of course it can't produce my desired frequencies, this is the reason why I had to make "a clock generator on my own". I
  14. Hi, I'm trying to tune Atlys HDMI Demo project so that HDMI output delivers a pure 74.25 MHz 720p signal and not 75 MHz as actually designed. To achevieve this goal, I designed a self made pcore to act as a clock generator. This "720p compliant clock generator" pcore is a simple vhdl/mpd file. Attached is a diagram of what this pcore does. Mainly it is supposedly using one sole CMT, implementing cascading two DCM_CLKGEN and one PLL_BASE. The idea was to replace the original clock generator of the design with this core. Instead of delivering 600Mhz and 75MHz outputs, it del