Simo47

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  1. Thank you guys for your answers. I solved my problem. It's stupid but I had a problem with my bitstream. simo
  2. Hey evryone ! i am using zybo 7010 in ubunto 16.04 I generate a BOOT.BIN and an image.ub, I put the two files in the SD card but it does not boot! in vivado i activate UART0 and UART1. jumper is good. I enclose the two files system-user.dtsi and system-conf.dtsi. my serial terminal is /dev/ttyUSB1. please helpe ! system-user.dtsi system-conf.dtsi
  3. Hi evryone ! I can't understand my problem, I have nothing on the console SDK. Knowing that I have the right driver and i successfully program FPGA and I'm on the right port. I am using Vivado 2016.2 ubunto linux and Zybo-z7-10 as board in vivado I create another project and I clean but the problem still persists ! plzz help ! I want just display a hello world with a simple a bitstream (Axi lite generated by vivado).
  4. Thank you for your reply. I have a bus register on 32 bit that i use it to control my data. What I am looking for is write on the same register several times. Else, I give PS values on this register in order to read them from PL side. I like the Verilog but I never did it, i am working in VHDL. I am using slv_reg3 for Control/Status Thank you process (S_AXI_ACLK) variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); begin if rising_edge(S_AXI_ACLK) then if S_AXI_ARESETN = '0' then slv_reg0
  5. Hey I have flags that I set from my PS soc. Know to read them from PL side I have an implementation error when I use the same register ! test1 <= slv_reg3(31); test2 <= slv_reg3(30); PSenable <= slv_reg3(29); Thank you
  6. Thanks for your reply, i will adapt it to my code. I'll keep you informed.
  7. I mean that the signals "ready" and "valid" both of them are at 1 for receiving one 32 bit via slv_reg1 ( i am using the GP0) the question is how we can put a delay betwen several 32 bits transaction ? thank u
  8. Tank you for your reply. I monitor the signals ready and valid that they are both to 1 when i receive data. But I still can not put a time delay between every 4 bytes I get
  9. I thank you very much for your reply and for your advice. You are right to said for better manage and control this bus it is necessary to implement its own bus AXI but for reasons of time I can not do it. I looked at your implementation it looks interesting but it is in Verilog, I have modules implemented in VHDL, so to adapt them it will take me a little time. I generate it with Vivado it is a simple AXI lite slave. I'd like you to look at it in more detail. Thank you for your time.
  10. Hey evryone ! I'm really stuck for a few days! I am sending 256 bits looped from my PS. But I think that I get juste the last 4 bytes of 8*4 that i send ! What I want from you is a few vhdl code line that allow me to receive all of my data (8 * 32 bits). You will find enclosed a photo of the result that I get Waiting for your reply. thank you I send my data on register 1 and I have to store it in ram Here a pseudo code c that allow me to send 8*32 bits: for(int i = 0; i < 8; i++){ Data_struct -> in = message[i] ; } the