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  1. @jpeyron Thank you very much! So as I expected, it was an output pin just like Vref. Then it is impossible that getting a temp conversion of -273.1ºC is because there's no power supply. I'll keep on doing more research.
  2. @artvvb I will be working in the range of 20 Hz - 300 kHz, so 300 kHz would be the maximum. Edit: forgot to mention it will be 2 bytes each transmission so that'd make it 16 * 20 = 320 bps (minimum) to 16 * 300k = 4.8 Mbps
  3. Hello. I was wondering which possible ways there are to connect 2 Zedboard. I read this thread about using an FMC-to-FMC cable and the OP was recommended to look at this. At the moment, I can't afford buying such cables so I was wondering if there are other ways?? I thought of using I2C to communicate one with another (I'd just need to get a few bits from the other Zedboard) but I'm clueless about which connection/pins I should use. Thanks in advance.
  4. @jpeyron Thank you! Please let me know when you get a response.
  5. @jpeyron So there's no actual difference if I feed it 1.8V with a power supply right? What the pin for, then? Thanks
  6. Hello guys. I was wondering how it is possible that the XADC in the Zedboard does actually convert data even though I didn't feed it with 1.8V power supply? I mean there is a physical pin but I'm not using it, so the XADC shouldn't work but it actually does. How come?Thanks.
  7. @jpeyron Hey! There's something I've noticed while running some tests. When using XADC + Xillybus, I open Hardware Manager in Vivado just to monitor the XADC. Temperature is always -273.1ºC and volts in VAUX0, VAUX8 and VP/VN is always 0.00. When I run your project, I use the Hardware Manager again to monitor and everything seems fine, temperature is at 30ºC and volts in VAUX0 looks great (even change when I put my finger on the pins, as expected). So I am starting there must be something wrong with the combo XADC + Xillybus although the XADC seems to do something, but it looks like it's always converting the same thing (although values change a little, implying is not stuck in the same result forever). I've been trying some things with the project you uploaded. I copied the whole XADC from your project to mine and tried it with Xillybus. Got the same result as described. I'm afraid there must be something wrong in the XADC. Currently, the constraints I'm using looks like: # XADC set_property -dict "PACKAGE_PIN L11 IOSTANDARD LVCMOS33" [get_ports "vp_in"]; set_property -dict "PACKAGE_PIN M12 IOSTANDARD LVCMOS33" [get_ports "vn_in"]; set_property -dict "PACKAGE_PIN E16 IOSTANDARD LVCMOS33" [get_ports "vauxn0"]; # "XADC-AD0N-R" set_property -dict "PACKAGE_PIN F16 IOSTANDARD LVCMOS33" [get_ports "vauxp0"]; # "XADC-AD0P-R" set_property -dict "PACKAGE_PIN D17 IOSTANDARD LVCMOS33" [get_ports "vauxn8"]; # "XADC-AD8N-R" set_property -dict "PACKAGE_PIN D16 IOSTANDARD LVCMOS33" [get_ports "vauxp8"]; # "XADC-AD8P-R" I actually tried to do it the way you have it set up in your constraints file like: # XADC set_property PACKAGE_PIN L11 [get_ports "vp_in"]; set_property PACKAGE_PIN M12 [get_ports "vn_in"]; set_property PACKAGE_PIN E16 [get_ports "vauxn0"]; # "XADC-AD0N-R" set_property PACKAGE_PIN F16 [get_ports "vauxp0"]; # "XADC-AD0P-R" set_property PACKAGE_PIN D17 [get_ports "vauxn8"]; # "XADC-AD8N-R" set_property PACKAGE_PIN D16 [get_ports "vauxp8"]; # "XADC-AD8P-R" But if I did that, I got an error when generating the bitstream that said there was some sort of conflict cause PS_GPIO[0] from Xillybus was LVCMOS33 and vauxn0 was LVCMOS18 on IO Bank 35. I don't really know what this means tho. Any clue on what might be going on? Thanks!
  8. I would if the project was coded in VHDL, but it's in Verilog and I'd to have to rewrite it first or learn Verilog and I don't have much time for either of the two at the moment. That's why I was asking if there was an easy way to do that in Verilog. Sorry [email protected]
  9. Hey @jpeyron Thanks for the project. Been testing it and I generated a bit file and programmed the FPGA. I only got results in Channel 1 and Channel 0 (channel 9 and 8 were always 0.000). I was wondering if there's any chance I can print those values in hex instead of decimal?
  10. @jpeyron I don't know how to implement Xillybus using the demo app since it's all done with 'block design' and Xillybus is a nightmare when you open block design. So I just use a wizard to instantiate an XADC (I use DRP as interface option as opposed to AXI4Lite in the demo) and connect it to the FIFO. As I said, I'm getting values constantly but they're not correct. Is there a way I can connect the one I used in the demo? Cause that one is working right.
  11. Hello everyone. I'm using a Zedboard and I'm running Xillinux on it. I'm getting info from the XADC using Xillybus but the values I'm getting don't seem to make sense. I'm converting VP/VN, Vaux0P/Vaux0N and Vaux8P/Vaux8N. They're in bipolar mode. I'm just seeing what the values are without feeding them any voltage, just the noise. I'm getting values like 8200, 8A00, 7F00 and so. According to the XADC doc, only the 12 MSB contain actual information about the conversion, being the other 4 bits just for accuracy. So that'd make them 820, 8A0, 7F0... Translating that into voltages, it would be as if I was feeding it 500mV (when it's under 800h) or -500 mV (when it's over 800h). Reasonable values would start at least with a 0, like 073 for example. At first I thought I was getting these values because I wasn't feeding it with any actual voltage source, hence the random behaviour. But then I tried following this tutorial on how to set up the XADC just using block design (without using any embedded linux) and I got the values through serial port. I modified the helloworld.c from that tutorial so I could print the hex values of the conversion (the raw data was an u32 so I just typed %xl in the printf) and values where like 0740, 0d56, and so. Removing the last 4 bits, that'd make it 074, 0d5 which I think are very reasonable values for noise. So, should I be worried about the values I'm getting from Xillybus? Is that an expected behaviour because of the noise? Is something wrong with the way I'm using/instantiating my XADC? UPDATE: I have tried feeding the XADC and values from Xillybus keep the same while in that demo app (the tutorial I mentioned) I'm getting them correctly so I assume this something wrong with the XADC but I can't seem to know what. Might it be the offset?? Thanks in advance!
  12. Thank you! I already got it working, although I'm getting some weird values from the XADC now. I'll make a new thread about it and see if you guys know something.
  13. (Not sure if this thread should go in Embedded Linux. If so, please feel free to move it) Hello everyone. I'm having quite a hard time trying to make these two (XADC and Xillybus/Xillinux) work together and I was hoping someone here could lend me a hand. Basically, what I am trying to achieve is: I'll input some analog signals to VP/VN, Vaux0 and Vaux8 to the XADC. I want it to convert them and that conversion to be written to a FIFO that can be read by Xillybus, which will make it available for me in Xillinux (so with a simple command I can dump the conversion into a file). A more visual way to explain this would be: Problem: I am getting nothing but zeros from Xillybus. How am I collecting this data? Xillinux comes with a few demo apps. I've modified one of them (streamread.c) so I can write whatever is reading to a file. So I connect to Xillinux via SSH and run this: touch output ./streamread /dev/xillybus_datastream output This output keeps getting bigger as long as streamread is running but as I said, there's nothing but 0000000... Info: I generated the XADC using the wizard so I guess everything is properly instantiated. Tests I've run so far: I've tried the XADC and Xillybus separately and they both work just fine. For the XADC, I followed this tutoral here and I managed to get readings from all inputs (and even temperature!) in spite of the fact that I wasn't even feeding it (all it was reading was noise). As for Xillybus, I tried a loopback FIFO where I could write something in the terminal and see it in a different one, so that worked good as well. Since XADC outputs 16-bit data, I had to create a new Xillybus project (I made it using the IP Core generator they have built in their website) to add a 16-bit-wide FIFO (actually, they had to be 2 since one is from host to FPGA and the other one from FPGA to host, although I'm only interested in the latter). I updated Xillybus accordingly and tested it by creating a simple VHDL that would send some characters to the FIFO if switch 1 was high. Worked like charm. I even used ./streamread /dev/xillybus_datastream output to make sure streamread was working properly and it was. This one I can't understand why is happening, but it's happening. I modified my VHDL code and used 4 LEDs of the Zedboard to see if the XADC was working good. So I took the last 4 bits of the conversion of the XADC and associated them with one LED each (LED0 with dout(0), LED1 with dout(1), and so on). They never turned on so the XADC was outputting zeros or it wasn't working at all. So I decided to do this: DRDY signal from XADC = LED1 and EMPTY flag from FIFO = LED2. LED1 was turned off the whole time (XADC wasn't converting) but to my surprise, EMPTY flag was always 1. I mean, that makes sense, if DRDY is never 1, it can't write to the FIFO (cause that DRDY acts as the wr_en for the FIFO) but then how am I getting so many zeros in Xillinux when using streamread? Isn't Xillybus supposed to not read from the FIFO if the EMPTY flag is high? I don't know what else to try, really. Hope you can guide me through this. If you need any more info like source code or something, I will gladly share it. Thank you (and sorry for the long post )
  14. Thank you @jpeyron I followed that tutorial and I got it working, meaning I must be doing something wrong when using XADC+Xillybus. I'll make a thread so more people can see it and maybe they can help me. Thank you again!
  15. Sorry for bothering you again guys, but I haven't been able to make it work. I'll try to explain what I've done so far and I'd really appreciate if any of you could shed some light on the problem. This is what my project looks like: I have run separate tests on the XADC and Xillybus, meaning that I created a testbench for the XADC which worked correctly and I also used the loopback fifo (width: 8 bits) that comes installed by default with Xillybus. So I put it all together and created a new Xillybus using their website to include 2 new fifos (one of them I won't be using it but it was required to create 2) that were 16 bits wide. I use the drdy signal from XADC as wr_en for the fifo and the output from the XADC is the data_in of the FIFO. I am writing the output of the fifo using the streamread C program included with Xillybus that let me read from the FIFOs. I edited it so it could write to a file so I'm saving all the data in binary mode then I open it using a hex editor. As long as it's running, the file being written increases its size but it's full of 0s, as if the XADC wasn't converting at all. I'm not sure if you're familiar with Xillybus, if you are you might point out what I am doing wrong? If you're not, I'd appreciate it if you told me how to get some test readings from XADC as the one you @jpeyron or @Sam Bergami showed in your screenshots. What program are you running? The one that outputs the temperature and the Vaux8 voltage. I tried running @jpeyron .bit (included in the zip you uploaded) but I wasn't successful on getting it working. I got a few erros when I opened it in Vivado and couldn't properly load the .bit file in the Zedboard. Thank you!