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  1. @artvvb I feel like I'm learning a lot, but there are still some things I'm unclear about: 1) On line 369, I see 2'h1. Is that the address that slv_reg1 was using? Why use two addresses for the same slv_reg0? Also, I don't understand what you did that makes it read only. 2) Sort of the same question. I'm still trying to make the connection as to how dumping the contents of slv_reg0 in the case of 2'h1 in addition to 2'h0 leads to setting up read-only and write-only registers
  2. @artvvb 1) What was the reason behind not using slv_reg1 in your design? Also, I noticed you did not comment out the "slv_reg1 <= 0;" part on line 218 or the "slv_reg3 <=0" on line 220 of the AXI file. Why? 2) What was the reason behind dumping the contents of slv_reg0 in the case of 2'h1 in addition to 2'h0 (i.e. why twice)? 3) It looks like you chose slv_reg2 for the LEDs. So that means I should be able to do something like Xil_Out32(BASEADDR+8, 0x00001001) if I want to light the 1st and 4th LEDs then right? Suppose I want to turn on the LED if I flip a switch. Could I replace the user logic with assign led = sw; so that I could avoid using the SDK to set it if I wanted to?
  3. @artvvbSo the slices I see are part of Vivado's IP catalog, but how do you get the two RTL blocks you have on there. Is that custom IP?
  4. @[email protected]'ve created my own IP before, so that's not an issue. What I would like is for this IP to interact with some Verilog code I have written (for instance, use AXI4 to read/write to a register in the Verilog code I wrote). I know that I can use xparameters.h to find registers in my custom IP I can read/write using Xil_Out/Xil_In. Maybe there's a way to feed that into a register in Verilog. I mean that gets turned into something on the FPGA anyways. I just don't know how to write/read to it.
  5. I was hoping that the port called "usb_uart" could somehow tie into the register in the verilog code I want to read from. So I named it "usb_uart" wiith the hope that the two would somehow communicate. I would like to read and write values to this register I named "usb_uart" using software on my PC. I just don't know what interface I can use to accomplish this. Vivado SDK and @[email protected]'s debug bus seem to be two ways to do it.
  6. What I want is to create a design where the matrix multiplication is implemented in verilog code (i.e. the FPGA itself does the calculation), but the values of the matrices can be read/written from/to a register (e.g. the register I named "usb_uart) in realtime (i.e. after the bitstream has been written to the FPGA) with some sort of software.
  7. @jpeyron, @[email protected], @artvvb I have this register in verilog code called usb_uart and I have a UART IP that maps to something called usb_uart Is there a way to use Vivado SDK or some other software to read/write the value of this register?
  8. @[email protected] So for whatever reason, the matrix multiplication from the prior version would return the zero matrix in simulation. So I decided to scrap the design and start over. I started off with the most basic part (the matrix multiplication) and got that working. I didn't hardcode the values like I did before. I put them in the testbench instead. When I ran the simulation, I get the correct result, but again, no delay. Is it even possible to get some sort of delay in a simulation without using physical parts? You mentioned clocks. I tried that with a prior simulation, but I still got no delay I also tried your debugging bus and ran into some issues as I followed your tutorial: http://zipcpu.com/blog/2017/06/29/sw-dbg-interface.html The big one is that there is no makefile in ~/filepath/dbgbus. I ended up compiling each individual makefile and got it to work, but still, what you say in the tutorial doesn't work when you try it. I also tried writing to the BRAM named "MEM," but that register wasn't recognized. I think it's because earlier on in the tutorial there was source code I need to have written prior to testing it. How do I build a design where I can get some sort of delay that would be comparable to real life? The issue seems to be the compiler makes it so the design doesn't need to do the calculation, so you mentioned externally feeding the FPGA values, but how is that possible in a simulation? I can do it with Vivado SDK easily, but that's in realtime. The simulation is important, but how can I get reasonable data if the compiler is preventing the very behavior I want to examine? Verilog files are attached. Mult_AB_tb.v Mult_AB.v
  9. @[email protected] From reading your website, you seem to be a fan of simulation: So I decided to simulate my design (even though I know it already works). I wrote the testbench and simulated it. What I want to happen is this: when the MMult_AB and Z switches are turned on (and A and B are off), the FPGA should multiply matrices A and B, check to see if the results are correct, and light an LED if they are. What the simulation says however, is that once MMult_AB and Z are both on, the LED automatically lights up (i.e. no delay). Of course, there must be some sort of delay, but this is not shown in the simulation. So how do you measure the delay? MMultAB_tb.v MMultAB.v
  10. @artvvb All I really did is put mytestip and Microblaze on it. I'm wondering why it isn't complaining that I haven't assigned a switch to A,B,Z, and MMult_AB. That's kinda what I don't get about it. I'm making a hybrid model of sorts. If instead I write it with just verilog, then when I go to implement the device, it asks me what switch I want to use (I didn't specify an .xdc file intentionally). In the past, if I wanted to use a switch, I could do that by adding the switch IP to the block design. I'm not really sure what to do if I want to combine the approaches.
  11. @artvvb Second attempt. I added signals to the already existing myiptest_v1_0_S00_AXI_inst and changed some names in myiptest of ports I got working in my original verilog design. The IP will synthesize, but I'm still not getting anything that is saying I need to specify a switch in the implementation phase. It is complaining about diff_clock_rtl_p not being implemented though. MMultAXI4v remains unchanged. myiptest_v1_0_S00_AXI.v myiptest_v1_0.v
  12. @artvvb Here is my first attempt at implementing your suggestion. After putting this IP in a block design however, it does not prompt me to select pins for switches and LEDs. You had mentioned I need to edit both AXI files. I usually only edit the myipname_v1_0_S00_AXI.v. I tried to copy and paste my changes from this AXI file to myiptest.v, but I get an error because myiptest.v does not have the slave registers I need, so I left that entire section blank. Where do I go from here? MMultAXI4v myiptest_v1_0_S00_AXI.v myiptest.v
  13. @[email protected] It doesn't even have to be on one IP. I just need to figure out a block design to where the FPGA has an AXI4 interface where a user can use VIvado SDK to change values, but the matrix multiplication itself is triggered by flipping a switch, and preferably the switch is not being monitored by Vivado SDK. I'm interested in minimizing the time it takes for the user to hit a switch to start the multiplication and if I have Vivado SDK monitor the switch, then that adds extra time.
  14. @[email protected] Thank you for the link to Verilator. I was looking for something like this. I will look the rest of you points at a later time, but you should know that my intention wasn't to leave Vivado SDK, but rather, build an IP that has a switch that uses the logic on-board the FPGA to multiply two matrices independently of Vivado SDK. Since it requires an AXI4 interface, I will still need to use VIvado SDK because I will be using it to change the values of the matrices during runtime. However, I also want to multiply the contents of A and B by flipping a switch and this is the part of the design that should not rely on Vivado SDK. Unfortunately, I know of no way to combine the two requirements, which is why I am asking for help.