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Everything posted by Korken

  1. Hi, I think I am having the same issue as others here. While I was programming a custom FT232H based board, I had my HS-2 programmer connected as well - and now it shows up with the same configuration as my custom board. Is there a way to restore my HS-2 programmer? Thanks for any assistance!
  2. @Fields With the measured rising/falling edges of about 1 ns I'd say 500 MHz is going to be a challenge. But it could also be that my scope can't measure that fast (as it is only 500 MHz).
  3. Thank you for the answer, then it is as I suspected. I also noticed that you can force the tool to use a "normal" I/O for clock input by specifying that in the XDC, but it was generally not recommended.
  4. Hi all, I am implementing a simple parallel interface to an FT232H from FTDI to use the 60 MHz 8-bit parallel interface for training VHDL. While doing this a question popped up that I was unable to find answer to, the FT232H delivers a sampling clock to which all signals are synchronous - when sampling signals to this clock does this clock have to be routed to an MRCC pin or not? It seems that MRCC pins should be used for global clocks, but what about sampling clocks? Thanks for any clarification!
  5. No problem, I understand that internal discussions sometimes cannot be shared.
  6. Hi again @jpeyron, Have there been any thoughts / discussions internally yet? I would very much like to know their view on pros / cons / worries. Best regards, Emil
  7. Hi all and Digilent representatives! I am a "long" user of the Cmod A7 and am quite pleased with it, except for the choice of SRAM. And on the side I have been playing with another RAM that is easy to use, delivers better performance (about 200 MB/s for the 3.3v version), and more space (8Mbyes) which would be a really nice update to the Cmod-A7. The new "HyperRAM" (http://www.digikey.com/products/en/integrated-circuits-ics/memory/774?k=hyperram&k=&pkeyword=hyperram&pv142=133&FV=ffe00306%2C1c0011&mnonly=0&newproducts=0&ColumnSort=0&page=1&stock=1&am
  8. Hi again, I have received the board and have tested using the standard 200 ohm series resistors and 33 ohm replacements on a 100 MHz signal. What I did was simply to forward the input 100 MHz clock on the Arty to two output pins, one with the original series resistance on and one with my replacement. This was measured with an 16:1 passive (resistive) probe which presents itself as an load of about 800 ohms (made from an 750 resistor + coax), with a 50 ohm input termination on the scope (the image show 1Meg, this is from another channel). The results, as can be seen in the images,
  9. Thank you for taking the time to check and give a lot of information! What would be the problem with the standard I/O headers on top? 72 MHz is not a high frequency, and taking standard rules of thumb for "when to think RF / impedance" (10x frequency & 1/10 of that wavelength in the medium) gives that any trace under a total length of 5 cm needs no high frequency considerations, this is why I was asking about the capacitance vs resistance. But great that the resistors are easily accessible, then I can reduce them significantly for my purpose. The Arty is in the perfect price/
  10. Hi all, We are looking to use the Arty board for first tests on a machine vision system we are developing, which runs a 72 MHz parallel interface. For ease of testing I was planning to use the Arty board and its I/Os, but I see that it has 200 Ohm series resistors on each pin which will put a limit on the max allowed switching speed. Are there any specifications on the pins when it comes to speed? With 200 Ohms about 5-8 pF is maximum allowed after the resistor for a 72 MHz signal. Else, as I do not have the board yet, are the resistors easy to get to (silkscreen designators for
  11. Thanks for the info! The 80 Ohms are a little difficult, I will have to add some impedance matching resistors but no problem. The camera has 115 Ohm out (due to a design decision) so two 18 Ohm resistors will be enough to get close to matched impedance. I will post some results as soon as I have them!
  12. Thank you! Then I know where to start I am not overly worried about the PMOD itself, I have tried 1.5 GBit/s over a standard 0.1" header and that worked like a charm (though I do not know how good the eye was, but no but errors). Please come back with the length of each pair, it will help me greatly!
  13. Thank you for the support! Best regards, Emil
  14. If you want to learn AXI and how to access the DDR3 memory, I recommend these videos: https://www.youtube.com/user/mamsadegh2/videos Extremely good and well made, perfect for starting with the Zynq!
  15. Hi all, I am working on a project where the plan is that I will interface a camera module to the ZYBO for testing a few algorithms in HW. The problem I just noticed is, though the ZYBO says it supports "LVDS", it has 3.3v on the BANKs where the high speed PMOD goes. Is it still possible to use it for LVDS input? I have 4x 340 MBit/s LVDS pairs with 2 clock + 2 data coming from 2 cameras. I read on the Xilinx forum that it should probably work, but will something strange happen to the input termination? The second thing I cannot find is if the LVDS pairs on the ZYBO that goes to a connector are
  16. Korken

    Xdc Constraints Errors?

    Okey, I made a last resort try. I changed the HDL wrapper for the block design to be VHDL (which I am more comfortable with), generated the bitstream and programmed the Zynq. And poof, everything is working! If I change back to the Verilog wrapper it stops working again. I could reproduce both on 100% new projects as well. Not sure what is making it go strange but I found a workaround.
  17. Korken

    Xdc Constraints Errors?

    Okey, I found the problem. It comes from the block editor not giving the interface the same name as I gave it. If you dig into the wrapper file the leds are defined as: led_tri_o[xxx] and defined as led[xxx] in the constraints file. Beginners mistake. With this fixed I can get 3/4 LEDs to light up when I connect it to a constant (not GPIO block) which is strange. I just used a size 4 constant vector block to connect to the LEDs and 3 of 4 light up. If I just pretend I didn't see that I tried to access the LEDs using the GPIO example from the Zynq Book, however no LEDs light up
  18. Hi, to my understanding (and I hope someone can clarify if I say something wrong): --- The board_part.xml This is used to define IO signal names, voltages and IO standard on the board so you can find then in the Block Editor. -- The ZYBO_zynq_def.xml This is imported to the Zynq IP after you have added it. Just double click it and there is a button for it at the top. This will configure the Processing System (PS) to work with all the external pars. For example it sets up the DDR delays, MIO IO type/Slew rates/Pull ups and so on. So to summarize you need the ZYBO_zynq_def.xml to
  19. Hi, follow this tutorial: https://reference.digilentinc.com/vivado:boardfiles This worked for me.
  20. Nice work and really easy to use! I agree that some standard AXI IP templates would be nice, but you have started sooooo......
  21. Korken

    Xdc Constraints Errors?

    I believe so. Code from constraints file: ##LEDs ##IO_L23P_T3_35 set_property PACKAGE_PIN M14 [get_ports {led[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] ##IO_L23N_T3_35 set_property PACKAGE_PIN M15 [get_ports {led[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] ##IO_0_35 set_property PACKAGE_PIN G14 [get_ports {led[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] ##IO_L3N_T0_DQS_AD1N_35 set_property PACKAGE_PIN D18 [get_ports {led[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] My system: Can you see something wrong? If you want
  22. Hi all, I have been following the Zynq Book for learing the Zynq and I have a ZYBO board. When I try to implement a design I always get 8 errors as: "[Common 17-55] 'set_property' expects at least one object. ["ZYBO_Master.xdc":48]". These errors are where I have uncommented the LED set_property lines. Could someone explain to me what this means and how I fix this? I am using Vivado 2014.4 on a Win7 Pro 64-bit machine. Link to ZIPed project: https://www.dropbox.com/s/las31dn5jceqgzi/first_zynq_design.zip?dl=0 Thank you for your time! Best Regards Emil, Sweden
  23. Hi, Thank you for taking the time!
  24. Hi, I too have this problem, I was planning to use this in a course but the upgrade spits a lot of errors. Is there any upgraded version available Digilent? Thanks! Edit: I am running Vivado 2014.4. Best Regards Emil Fresk LuleƄ University of Technology Sweden