Korken

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  1. Thank you for the answer, then it is as I suspected. I also noticed that you can force the tool to use a "normal" I/O for clock input by specifying that in the XDC, but it was generally not recommended.
  2. Hi all, I am implementing a simple parallel interface to an FT232H from FTDI to use the 60 MHz 8-bit parallel interface for training VHDL. While doing this a question popped up that I was unable to find answer to, the FT232H delivers a sampling clock to which all signals are synchronous - when sampling signals to this clock does this clock have to be routed to an MRCC pin or not? It seems that MRCC pins should be used for global clocks, but what about sampling clocks? Thanks for any clarification!
  3. No problem, I understand that internal discussions sometimes cannot be shared.
  4. Hi again @jpeyron, Have there been any thoughts / discussions internally yet? I would very much like to know their view on pros / cons / worries. Best regards, Emil
  5. Hi all and Digilent representatives! I am a "long" user of the Cmod A7 and am quite pleased with it, except for the choice of SRAM. And on the side I have been playing with another RAM that is easy to use, delivers better performance (about 200 MB/s for the 3.3v version), and more space (8Mbyes) which would be a really nice update to the Cmod-A7. The new "HyperRAM" (http://www.digikey.com/products/en/integrated-circuits-ics/memory/774?k=hyperram&k=&pkeyword=hyperram&pv142=133&FV=ffe00306%2C1c0011&mnonly=0&newproducts=0&ColumnSort=0&page=1&stock=1&quantity=0&ptm=0&fid=0&pageSize=25) is like a combination between DDR and SRAM, this blog post describes quite nicely (with later posts showing implementation): https://warmcat.com/embedded/hardware/hyperbus/2016/09/02/hyperram.html What is Digilent's view/thoughts on the usage of HyperRAM instead of the (aging) SRAM? A quick check seems to suggest that it is about half the price of the SRAM currently used as well. I hope for a fruitful discussion. Best regards!
  6. Hi again, I have received the board and have tested using the standard 200 ohm series resistors and 33 ohm replacements on a 100 MHz signal. What I did was simply to forward the input 100 MHz clock on the Arty to two output pins, one with the original series resistance on and one with my replacement. This was measured with an 16:1 passive (resistive) probe which presents itself as an load of about 800 ohms (made from an 750 resistor + coax), with a 50 ohm input termination on the scope (the image show 1Meg, this is from another channel). The results, as can be seen in the images, the 200 ohm pin still performs quite okey, though it was very sensitive to anything coming close or touching the board. The 33 ohm signal was rock solid. So I will continue and replace all the I/O resistors to 33 ohm, something a little bigger could probably be used as well but I have a lot of 33 ohm resistors. But is shows that the Arty has no problem, what so ever, with single ended signals up to 100 MHz so far. Another 2 cm of signal path will be added when I add my board, but this should not have any large effect on signal integrity at these speeds. Plus I have looked around the headers for GND points where I will solder extra GND paths, so there won't be a deficiency. @jpeyron Thanks for the signal lengths and the assistance! 200 Ohm: 33 Ohm: Probe:
  7. Thank you for taking the time to check and give a lot of information! What would be the problem with the standard I/O headers on top? 72 MHz is not a high frequency, and taking standard rules of thumb for "when to think RF / impedance" (10x frequency & 1/10 of that wavelength in the medium) gives that any trace under a total length of 5 cm needs no high frequency considerations, this is why I was asking about the capacitance vs resistance. But great that the resistors are easily accessible, then I can reduce them significantly for my purpose. The Arty is in the perfect price/performance range for general prototyping, even for cameras. Another question, is there a table of trace lengths FPGA -> I/O 1-40, or if it is possible to generate it? Just something rough. Just to take the ones that have about the same length / to compensate on my adapter board. It shouldn't really matter, but I like to play it safe. Thanks for all the help!
  8. Hi all, We are looking to use the Arty board for first tests on a machine vision system we are developing, which runs a 72 MHz parallel interface. For ease of testing I was planning to use the Arty board and its I/Os, but I see that it has 200 Ohm series resistors on each pin which will put a limit on the max allowed switching speed. Are there any specifications on the pins when it comes to speed? With 200 Ohms about 5-8 pF is maximum allowed after the resistor for a 72 MHz signal. Else, as I do not have the board yet, are the resistors easy to get to (silkscreen designators for correct identification) to replace the resistors manually with a lower value? Thank you for your time!
  9. Thanks for the info! The 80 Ohms are a little difficult, I will have to add some impedance matching resistors but no problem. The camera has 115 Ohm out (due to a design decision) so two 18 Ohm resistors will be enough to get close to matched impedance. I will post some results as soon as I have them!
  10. Thank you! Then I know where to start I am not overly worried about the PMOD itself, I have tried 1.5 GBit/s over a standard 0.1" header and that worked like a charm (though I do not know how good the eye was, but no but errors). Please come back with the length of each pair, it will help me greatly!
  11. Thank you for the support! Best regards, Emil
  12. If you want to learn AXI and how to access the DDR3 memory, I recommend these videos: https://www.youtube.com/user/mamsadegh2/videos Extremely good and well made, perfect for starting with the Zynq!
  13. Hi all, I am working on a project where the plan is that I will interface a camera module to the ZYBO for testing a few algorithms in HW. The problem I just noticed is, though the ZYBO says it supports "LVDS", it has 3.3v on the BANKs where the high speed PMOD goes. Is it still possible to use it for LVDS input? I have 4x 340 MBit/s LVDS pairs with 2 clock + 2 data coming from 2 cameras. I read on the Xilinx forum that it should probably work, but will something strange happen to the input termination? The second thing I cannot find is if the LVDS pairs on the ZYBO that goes to a connector are length matched. Are they? If not, what is the length difference so I can compensate on my side. Sure, 340 MBit/s is low, but I like to have everything correct when working with LVDS. Thanks for your time! Best regards, Emil
  14. Okey, I made a last resort try. I changed the HDL wrapper for the block design to be VHDL (which I am more comfortable with), generated the bitstream and programmed the Zynq. And poof, everything is working! If I change back to the Verilog wrapper it stops working again. I could reproduce both on 100% new projects as well. Not sure what is making it go strange but I found a workaround.