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  1. Arty: I/O, max switching speed of the signals?

    Thank you for taking the time to check and give a lot of information! What would be the problem with the standard I/O headers on top? 72 MHz is not a high frequency, and taking standard rules of thumb for "when to think RF / impedance" (10x frequency & 1/10 of that wavelength in the medium) gives that any trace under a total length of 5 cm needs no high frequency considerations, this is why I was asking about the capacitance vs resistance. But great that the resistors are easily accessible, then I can reduce them significantly for my purpose. The Arty is in the perfect price/performance range for general prototyping, even for cameras. Another question, is there a table of trace lengths FPGA -> I/O 1-40, or if it is possible to generate it? Just something rough. Just to take the ones that have about the same length / to compensate on my adapter board. It shouldn't really matter, but I like to play it safe. Thanks for all the help!
  2. Hi all, We are looking to use the Arty board for first tests on a machine vision system we are developing, which runs a 72 MHz parallel interface. For ease of testing I was planning to use the Arty board and its I/Os, but I see that it has 200 Ohm series resistors on each pin which will put a limit on the max allowed switching speed. Are there any specifications on the pins when it comes to speed? With 200 Ohms about 5-8 pF is maximum allowed after the resistor for a 72 MHz signal. Else, as I do not have the board yet, are the resistors easy to get to (silkscreen designators for correct identification) to replace the resistors manually with a lower value? Thank you for your time!
  3. Zybo LVDS input to the High-Speed PMOD?

    Thanks for the info! The 80 Ohms are a little difficult, I will have to add some impedance matching resistors but no problem. The camera has 115 Ohm out (due to a design decision) so two 18 Ohm resistors will be enough to get close to matched impedance. I will post some results as soon as I have them!
  4. Zybo LVDS input to the High-Speed PMOD?

    Thank you! Then I know where to start I am not overly worried about the PMOD itself, I have tried 1.5 GBit/s over a standard 0.1" header and that worked like a charm (though I do not know how good the eye was, but no but errors). Please come back with the length of each pair, it will help me greatly!
  5. Zybo LVDS input to the High-Speed PMOD?

    Thank you for the support! Best regards, Emil
  6. How to use the DDR on Zybo

    If you want to learn AXI and how to access the DDR3 memory, I recommend these videos: https://www.youtube.com/user/mamsadegh2/videos Extremely good and well made, perfect for starting with the Zynq!
  7. Zybo LVDS input to the High-Speed PMOD?

    Hi all, I am working on a project where the plan is that I will interface a camera module to the ZYBO for testing a few algorithms in HW. The problem I just noticed is, though the ZYBO says it supports "LVDS", it has 3.3v on the BANKs where the high speed PMOD goes. Is it still possible to use it for LVDS input? I have 4x 340 MBit/s LVDS pairs with 2 clock + 2 data coming from 2 cameras. I read on the Xilinx forum that it should probably work, but will something strange happen to the input termination? The second thing I cannot find is if the LVDS pairs on the ZYBO that goes to a connector are length matched. Are they? If not, what is the length difference so I can compensate on my side. Sure, 340 MBit/s is low, but I like to have everything correct when working with LVDS. Thanks for your time! Best regards, Emil
  8. Xdc Constraints Errors?

    Okey, I made a last resort try. I changed the HDL wrapper for the block design to be VHDL (which I am more comfortable with), generated the bitstream and programmed the Zynq. And poof, everything is working! If I change back to the Verilog wrapper it stops working again. I could reproduce both on 100% new projects as well. Not sure what is making it go strange but I found a workaround.
  9. Xdc Constraints Errors?

    Okey, I found the problem. It comes from the block editor not giving the interface the same name as I gave it. If you dig into the wrapper file the leds are defined as: led_tri_o[xxx] and defined as led[xxx] in the constraints file. Beginners mistake. With this fixed I can get 3/4 LEDs to light up when I connect it to a constant (not GPIO block) which is strange. I just used a size 4 constant vector block to connect to the LEDs and 3 of 4 light up. If I just pretend I didn't see that I tried to access the LEDs using the GPIO example from the Zynq Book, however no LEDs light up when using it. At this point I am at a loss. I'm not sure how to continue as it works (or 3 of 4 LEDs work) with a constant but not when connected to a GPIO block. How would you start to attack this problem? EDIT: Even more strange, if I create a standalone VHDL file that lights up the last LED it works, but not when I use the constants block... Very strange.
  10. Zybo Board Definition For Vivado?

    Hi, to my understanding (and I hope someone can clarify if I say something wrong): --- The board_part.xml This is used to define IO signal names, voltages and IO standard on the board so you can find then in the Block Editor. -- The ZYBO_zynq_def.xml This is imported to the Zynq IP after you have added it. Just double click it and there is a button for it at the top. This will configure the Processing System (PS) to work with all the external pars. For example it sets up the DDR delays, MIO IO type/Slew rates/Pull ups and so on. So to summarize you need the ZYBO_zynq_def.xml to set up the IP core and the board_part.xml is just a definition of interfaces. This could however be wrong as the board_part.xml calls an TCL script and looking at it it seems to do the same as ZYBO_zynq_def.xml. However my strongest point is not in TCL. This is how I have understood it from looking at the XMLs and playing around a bit. But I can be wrong. Perhaps Digilent could clarify?
  11. Zybo Board Definition For Vivado?

    Hi, follow this tutorial: https://reference.digilentinc.com/vivado:boardfiles This worked for me.
  12. Nice work and really easy to use! I agree that some standard AXI IP templates would be nice, but you have started sooooo......
  13. Xdc Constraints Errors?

    I believe so. Code from constraints file: ##LEDs ##IO_L23P_T3_35 set_property PACKAGE_PIN M14 [get_ports {led[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] ##IO_L23N_T3_35 set_property PACKAGE_PIN M15 [get_ports {led[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] ##IO_0_35 set_property PACKAGE_PIN G14 [get_ports {led[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] ##IO_L3N_T0_DQS_AD1N_35 set_property PACKAGE_PIN D18 [get_ports {led[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] My system: Can you see something wrong? If you want to have a thorough look the project is linked in the first post. Best Regards Emil
  14. Xdc Constraints Errors?

    Hi all, I have been following the Zynq Book for learing the Zynq and I have a ZYBO board. When I try to implement a design I always get 8 errors as: "[Common 17-55] 'set_property' expects at least one object. ["ZYBO_Master.xdc":48]". These errors are where I have uncommented the LED set_property lines. Could someone explain to me what this means and how I fix this? I am using Vivado 2014.4 on a Win7 Pro 64-bit machine. Link to ZIPed project: https://www.dropbox.com/s/las31dn5jceqgzi/first_zynq_design.zip?dl=0 Thank you for your time! Best Regards Emil, Sweden