RajatRao

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Everything posted by RajatRao

  1. Hi @D@n, Yes the MIG IP does have the configurability. Unfortunately, I'm not using MIG - I'm using Zynq which has an in-built DDRC. I don't think the Zynq DDRC can be configured, can it? Any ideas? Thanks, Rajat Rao
  2. Thanks for pointing me to those tutorials. The tutorials explain how to create an IP with AXI4 interface. I am quite familiar with this. In this case, the IP created will have its own address space because it needs to be addressable. However, the IP I am looking to create should behave similar to the AXI interconnect. It just forwards AXI transactions from one port to the other. This means that it should not have an address space of its own. Specifically, I'm looking for what settings to change in IP packager that will allow me to do this. The AXI interconnect port has Type 'hier'. Maybe this needs to be set somewhere, but I don't know where or how. Thanks, Rajat Rao
  3. Hello, I am trying to create an IP that reorders AXI DRAM addresses, similar to the one described in Xilinx xapp792. The main purpose is to change from Row/Bank/Column to Bank/Row/Column addressing. A portion of the block design where the IP will be used is attached. When I create this IP, it gets its own address space. However, it should only be a forwarder, like the axi interconnect. I know I should be setting some parameters in IP packager, but I don't know what those are. Can anyone help me out with this? Thanks, Rajat Rao
  4. Hello, On Pg 12 of the Pynq schematic, the following information is mentioned 1V -> 1.6A 3.3V -> 2.6A 1.8V -> 1.8A 1.5V -> 1.8A What exactly does this mean? Is it the maximum current consumption on the respective voltage levels? If yes, how is the current on 1.5V line so high when it is only connected to the DDR section? Thanks, Rajat Rao
  5. I have made some progress since I posted the question. 1,2) The clock problem was due to connecting the axilite interface and the video streaming interface to different clock domains. Once I connected both to clk1 of the reference design, it works smoothly. The HLS IP was inserted between the video streaming IP and the AXI VDMA IP. I would still like to have an educated opinion on the best way to do video processing. 3) I would still appreciate if someone could tell me how to upgrade the design without the relevant Vivado version. A huge thank you to Digilent for providing such an excellent demo (hdmi_in for Arty Z7). It really helped me learn a lot.
  6. Hello, I have a Arty-Z7-20 board and got the hdmi_in demo working on it. I need to process the incoming hdmi stream and I found that doing it as an application on Zynq is too slow because pixel accesses are required. I would like to use the OpenCV functions in HLS to do this. I wrote the following program in HLS - #include <hls_video.h> void video_resize(hls::stream< ap_axiu<24,1,1,1> > &video_in, hls::stream< ap_axiu<24,1,1,1> > &video_out) { #pragma HLS INTERFACE axis port=video_in bundle=INPUT_STREAM #pragma HLS INTERFACE axis port=video_out bundle=OUTPUT_STREAM hls::Mat<1080, 1920, HLS_8UC3> src; hls::Mat<1080, 1920, HLS_8UC3> dst; #pragma HLS dataflow hls::AXIvideo2Mat(video_in, src); hls::Scale(src, dst, 2.0, 0.0); //Simple processing hls::Mat2AXIvideo(dst, video_out); } My questions are - 1) Where in the demo block design should I connect this? (a) Between the video-to-axi4-stream ip and the axi-vdma ip (b) Add 1 more axi-vdma IP with both read and write channels and connect to it (c) Some better alternative? 2) In HLS, this design was synthesized with a clock constraint of 6.7 ns, so it meets the HDMI clock constraint of 148.5 MHz. However, in IP Integrator, a default value of 100 MHz is taken and I am unable to change this. What is the solution? 3) Is there any Digilent reference design/demo that already has HLS OpenCV IP integrated into the block design? Xilinx provides XAPP1167, but this only compiles on 2014.4 version which I don't have. I don't know how to upgrade the design to the current version. I might be asking too much, but any help is appreciated. Thanks, Rajat Rao