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$ git worktree add ../Zybo-Z7-20-pcam-5c_2018_2 v2018.2-2 $ cd ../Zybo-Z7-20-pcam-5c_2018_2/ $ git submodule init $ git submodule update $ python digilent-vivado-scripts/git_vivado.py checkout Warning: Files and directories contained in C:/git/Zybo-Z7-20-pcam-5c_2018_2/proj may be overwritten. Do you wish to continue? Y/N? Y Checking out project Zybo-Z7-20-pcam-5c_2018_2.xpr from repo Zybo-Z7-20-pcam-5c_2018_2 ****** Vivado v2018.2 (64-bit) **** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. Sourcing tcl script 'C:/Users/rogyorge/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl' INFO: [Common 17-1463] Init.tcl in C:/Users/rogyorge/AppData/Roaming/Xilinx/Vivado/init.tcl is not used. Vivado_init.tcl is already sourced. source C:/git/Zybo-Z7-20-pcam-5c_2018_2/digilent-vivado-scripts/digilent_vivado_checkout.tcl -notrace INFO: Creating new project "Zybo-Z7-20-pcam-5c_2018_2" in C:/git/Zybo-Z7-20-pcam-5c_2018_2/proj create_project: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 350.289 ; gain = 119.281 INFO: Capturing board information from C:/git/Zybo-Z7-20-pcam-5c_2018_2/project_info.tcl INFO: Configuring project IP handling properties INFO: Setting IP repository paths INFO: Refreshing IP repositories INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/git/Zybo-Z7-20-pcam-5c_2018_2/repo'. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.2/data/ip'. update_ip_catalog: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 408.137 ; gain = 57.848 INFO: Adding HDL sources INFO: Adding XCI IP sources INFO: Adding constraints INFO: Rebuilding block design from script INFO: [BD_TCL-3] Currently there is no design <system> in project, so creating one... Wrote : <C:/git/Zybo-Z7-20-pcam-5c_2018_2/proj/Zybo-Z7-20-pcam-5c_2018_2.srcs/sources_1/bd/system/system.bd> INFO: [BD_TCL-4] Making design <system> as current_bd_design. INFO: [BD_TCL-5] Currently the variable <design_name> is equal to "system". INFO: [BD_TCL-6] Checking if the following IPs exist in the project's IP catalog: digilentinc.com:user:AXI_BayerToRGB:1.0 digilentinc.com:user:AXI_GammaCorrection:1.0 digilentinc.com:ip:MIPI_CSI_2_RX:1.1 digilentinc.com:ip:MIPI_D_PHY_RX:1.3 xilinx.com:ip:axi_vdma:6.3 xilinx.com:ip:clk_wiz:6.0 xilinx.com:ip:processing_system7:5.5 digilentinc.com:ip:rgb2dvi:1.4 xilinx.com:ip:proc_sys_reset:5.0 xilinx.com:ip:v_axi4s_vid_out:4.0 xilinx.com:ip:v_tc:6.1 xilinx.com:ip:xlconcat:2.1 . INFO: [BD_TCL-6] Checking if the following modules exist in the project's sources: DVIClocking . INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/git/Zybo-Z7-20-pcam-5c_2018_2/repo'. create_bd_cell: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 639.629 ; gain = 153.918 CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.073 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.034 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.03 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.082 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.073 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.034 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.03 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.082 . PS DDR interfaces might fail when entering negative DQS skew values. WARNING: [BD 41-1731] Type mismatch between connected pins: /DVIClocking_0/SerialClk(undef) and /rgb2dvi_0/SerialClk(clk) WARNING: [BD 41-1731] Type mismatch between connected pins: /DVIClocking_0/PixelClk(undef) and /rgb2dvi_0/PixelClk(clk) WARNING: [BD 41-1731] Type mismatch between connected pins: /DVIClocking_0/PixelClk(undef) and /rst_vid_clk_dyn/slowest_sync_clk(clk) WARNING: [BD 41-1731] Type mismatch between connected pins: /DVIClocking_0/PixelClk(undef) and /v_axi4s_vid_out_0/vid_io_out_clk(clk) WARNING: [BD 41-1731] Type mismatch between connected pins: /DVIClocking_0/PixelClk(undef) and /vtg/clk(clk) WARNING: [BD 41-1731] Type mismatch between connected pins: /DVIClocking_0/PixelClk5X(undef) and /video_dynclk/pxl_clk_5x(clk) WARNING: [BD 41-1731] Type mismatch between connected pins: /rgb2dvi_0/aRst_n(rst) and /v_axi4s_vid_out_0/locked(undef) Wrote : <C:/git/Zybo-Z7-20-pcam-5c_2018_2/proj/Zybo-Z7-20-pcam-5c_2018_2.srcs/sources_1/bd/system/system.bd> WARNING: [Coretcl 2-176] No IPs found WARNING: [BD 41-721] Attempt to set value '50000000' on disabled parameter 'C_S_AXI_LITE_FREQ_HZ' of cell '/MIPI_D_PHY_RX_0' is ignored WARNING: [BD 41-721] Attempt to set value '200000000' on disabled parameter 'kRefClkFreqHz' of cell '/MIPI_D_PHY_RX_0' is ignored CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.073 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.034 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.03 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.082 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.073 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.034 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.03 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.082 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.073 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.034 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.03 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.082 . PS DDR interfaces might fail when entering negative DQS skew values. INFO: [digilentinc.com:ip:MIPI_CSI_2_RX:1.1-17] /MIPI_CSI_2_RX_0Verified that video_aclk frequency can handle RxByteClkHS frequency. AXI-Stream bandwidth 600000000 Pix/s >= PPI bandwidth 134400000.0 Pix/s INFO: [digilentinc.com:ip:MIPI_D_PHY_RX:1.3-17] /MIPI_D_PHY_RX_0FREQ_HZ of 50000000 propagated into CONFIG.C_S_AXI_LITE_FREQ_HZ INFO: [digilentinc.com:ip:MIPI_D_PHY_RX:1.3-17] /MIPI_D_PHY_RX_0FREQ_HZ of 200000000 propagated into CONFIG.kRefClkFreqHz INFO: [digilentinc.com:ip:MIPI_D_PHY_RX:1.3-17] /MIPI_D_PHY_RX_0FREQ_HZ of 84000000 propagated onto RxByteClkHS Wrote : <C:/git/Zybo-Z7-20-pcam-5c_2018_2/proj/Zybo-Z7-20-pcam-5c_2018_2.srcs/sources_1/bd/system/system.bd> VHDL Output written to : C:/git/Zybo-Z7-20-pcam-5c_2018_2/proj/Zybo-Z7-20-pcam-5c_2018_2.srcs/sources_1/bd/system/synth/system.vhd VHDL Output written to : C:/git/Zybo-Z7-20-pcam-5c_2018_2/proj/Zybo-Z7-20-pcam-5c_2018_2.srcs/sources_1/bd/system/sim/system.vhd VHDL Output written to : C:/git/Zybo-Z7-20-pcam-5c_2018_2/proj/Zybo-Z7-20-pcam-5c_2018_2.srcs/sources_1/bd/system/hdl/system_wrapper.vhd make_wrapper: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 841.781 ; gain = 97.035 INFO: Configuring synth_1 run INFO: Setting current synthesis run INFO: Configuring impl_1 run INFO: Setting current implementation run INFO: Project created: Zybo-Z7-20-pcam-5c_2018_2 INFO: Exiting Vivado INFO: [Common 17-206] Exiting Vivado at Fri Nov 29 11:46:17 2019... Opened in Vivado proj/*.xpr, unticked CSI-2 Debug module and Generated Bitstream successfully.

1. I think it is either a failed project upgrade or the submodule commit being out of sync with the main repo. This should not happen in the 2018.2 release, which is why I recommend you try it. 2. Of course, that was the whole point of your question.

I did a git checkout v2017.4 and re-generated the Vivado project in 2017.4. It asked for IP upgrade and I had to create a wrapper for the block design manually (which I should not have had to do), but Synthesis and Implementation worked. Could you try the 2018.2 release too in Vivado 2018.2 and see if it works.