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Everything posted by elodg

  1. The skew demanded by the RGMII specs between clock and data groups has not been implemented on the PCB. See the trace lengths below (unit mm) for delay matching inside the signal groups. This implies that the skew must be implemented in the MAC and/or PHY. The PHY has internal delays that are configurable by pull resistors on pins 32 and 16: R88/83 and R72/79. The board is shipping with no PHY delays enabled as written in the reference manual: You may change these on your board. The reason for no delay matching by default is because of the flexibility in MAC implementation in the FPGA. Check the exact MAC IP for delay matching. If it is not readily configurable, enable it in the PHY instead.
  2. @Bert_ALSE, to work around the JTAG issue on the FMC adapter, you can try either shunting FMC_TDI to FMC_TDO on the FMC adapter OR interrupting the PRSNT_M2C_L connection to GND by pulling the pin from the FMC connector, for example. It is not for the faint-hearted, in any case. You mention Aurora and gigabit, so I assume you wish to use the GTP transceivers in the Artix-7 on the the Nexys Video. VADJ has absolutely no effect on the GTP transceivers. Just make sure you set it appropriately for any other control pins or interfaces using regular user I/O (non-GT) pins. You also mention VC707, which has GTX (GTZ?) transceivers. The data rates supported are obviously different, but there might be other functional differences as well. Make sure all the pre-emphasis and voltage swing settings are correct. DPx and GBTCLK pins go directly to the FPGA. The PCB traces are length-matched and designed for 100-ohm characteristic impedance. Via stub elimination was not considered necessary. The GT power supplies are within spec. The interface was validated using IBERT with an FMC loopback board at the maximum data rate supported by the FPGA.
  3. @qwaserdf, you are wrongly assuming that Vivado 2016.4 without SDK installed will work with SDK 2018.1. Because it does not, Vivado is giving you an error during project creation: "couldn't execute xsct...". Since that fails, you are left with an old hardware handoff (.hdf) in the sdk workspace. You are importing the same old hdf when creating a new hardware platform in the workspace. That explains why it is looking for an nonexistent DDYNCLK variable, which is for an IP that does not exist in the hardware project anymore. The rest of the SDK errors are due to the wrong SDK version. You can try importing the hdf from hw_handoff instead and go through with manually re-creating the BSP for 2018, but do yourself a favor and install SDK 2016.4 instead.
  4. @bklopp, you are getting version errors as expected. Use the Vivado version the project was published in and tested for. If you still want to do the upgrade yourself, this particular SDK error can be fixed by manually updating each driver and OS version to the current one, or re-creating the BSP and manually importing all the settings from the old one.
  5. The connection flow is the following: Sink (Zybo) asserts Hot-Plug Detect -> confirm that HDMI_HPD is tied high and HDMI_OUT_EN is unused or tied low. Source (whatever you have connected) queries the capabilities over DDC -> confirm that Digilent DVI appears as a secondary monitor on a PC for example. Source begins transmitting video -> confirm that the Source actually enables the secondary monitor and drives a compatible resolution. Sink locks onto the signal -> confirm that clk_wiz is locked and aPixelClkLckd goes high. v_vid_in_axi4s splits video data into timing and AXI-Stream -> confirm with ILA that tvalid goes high and timing signals fit your resolution. v_tc matches the timing signal to a known resolution and, if configured, re-generates the same timing on its output -> confirm with ILA. v_axi4s_video_out waits for Start-of-Frame (tuser) and enables the generator in v_tc -> confirm vtg_ce and locked go high. Video appears on VGA -> confirm hsync and vsync are correctly timed for the expected resolution.
  6. I just ran implementation on the Zybo-Z7-10-HDMI project and it completed bitstream generation. Don't throw me off the scent here! So the implementation error is given for the PLL in rgb2dvi being out-of-range, because it is driven by a 165MHz PixelClk and it multiplies it by 10 internally, which is outside the 1600MHz maximum for PLL. PixelClk needs to be constrained properly for your maximum resolution. For 1080p, you are shooting for 148.5MHz. In a pass-through design this clock is coming from dvi2rgb, so you want to make sure that the TMDS input clock is constrained. Add create_clock -period 6.734 -waveform {0 3.367} [get_ports { hdmi_in_clk_p }]; to your top-level XDC.
  7. @joaBaur, I don't think this is related to the IP rev, but rather default settings for the expected TMDS clock frequency. From the documentation: Also, 165MHz TMDS clock is way outside the Artix-7 FPGA's BUFIO/BUFR capabilities. You might want to lower that.
  8. We don't have a Z7 board, but we do have Arty Z7 and Zybo Z7. Check the HDMI section of the Zybo Z7 reference manual for auxiliary signals. Everything you described is sound, it is just missing HPD. Hot plug detect needs to be driven by RX high, so that your laptop can read the DDC and detect a display. Also, if the board has buffers, muxes on the data path, there might be an enable signal needed too.
  9. elodg

    HDMI In to VGA out on Zybo

    @cgarry, I recommend ug949 chapter 5 for instructions on how to achieve timing closure. You have to click on each failing category in the timing summary and see the failing paths on the right. For example, if you check the Pulse Width constraint, it is due to driving the BUFR primitive with a frequency too high for an Artix-7 FPGA. You may ignore this warning, or specify a larger period constraint for the HDMI input clock (hdmi_clk_p) and using a lower resolution. The rest of the timing categories have to be analyzed path-by-path. Solve Inter-Clock first, which are most of the time due to incorrect clock-domain crossings. Intra-Clock should be solved by reducing congestion, trying different implementation strategies or lowering clock frequencies.
  10. Hello Matthias, When you move from a software prototype to embedded hardware, you first need to think about how the implementation changes. Embedded systems have different performance/latency profiles and data access patterns are very important. See if you really need 8GB of memory for your algorithm. If yes, an FPGA board with SODIMM slot is your only viable choice. High-Bandwidth Memory is still expensive. I would start by researching the feasibility of your algorithm in hardware. Get to know FPGA architecture and write prototypes either in VHDL or HLS. The interfaces are secondary to algorithm. For Ethernet you will need a MAC and a microprocessor running an IP stack inside the FPGA. See if the latency of a Microblaze+lwIP combo is acceptable. Otherwise, you are left with implementing the IP stack in hardware that extracts the image data and spews it into memory. Similarly, for USB you will need a host controller. You either license an IP for FPGA or go with one of the ARM+FPGA hybrids (Zynq). The Zynq has both Ethernet MAC and USB controller included as hard cores, so you would only need to implement your processing algorithm in FPGA.
  11. @pbaran, I did some edits to the relevant sections of the Anvyl Reference Manual. To summarize: The microcontrollers are USB embedded hosts supporting keyboards and mice implementing the USB HID boot protocol. The rule of thumb is if it works in a BIOS setting, it should work with our boards too. Devices with USB/PS/2 dual functionality are still used in USB mode. The whole set of PS/2 commands are implemented, even keyboard output commands. I could not find the contradictions you mentioned with respect to PS/2 specs. The device (microcontroller) always drives the clock pulses, but the host can pull the line low in certain conditions. There is a programming header, so you can write your own firmware and program it with Microchip tools. The firmware source code is not public. State your case in an e-mail to support and we might give it to you provided certain legal requirements are met.
  12. On how to use the IP, check the countless examples available on our Github page, even if not specifically made for your board: https://github.com/search?q=org%3ADigilent+rgb2dvi&type=Code You can look at the block design and see where those signals are coming from. These are the synchronization signals adopted by DVI and HDMI from the analog world of television and VGA: http://www.cs.unc.edu/~stc/FAQs/Video/dvi_spec-V1_0.pdf The sync signals can be generated by the Xilinx IP Video Timing Controller. The actual timing parameters are defined in VESA and CEA specs, which are not free, but a quick web search will turn up something for sure. Also, here is a primer on VGA: https://learn.digilentinc.com/Documents/269
  13. Deciding which signals could share coupled traces is I/O interface dependent. For example, if it is a source-synchronous parallel interface, crosstalk is not an issue between bits of the same data bus. All bits that change rise or fall in the same time, momentarily inducing change on coupled bits too. It all stabilizes quickly by the time the sampling clock edge arrives. However clock is essential to be monotonic and not have spurious edges. So in this case I would make sure clock (if single-ended) is coupled with a GND trace.
  14. All Digilent FMC Carrier boards have User I/O pairs routed differentially, 100-ohm coupled. Artix-7 has HR banks, supporting LVDS_25 and many other differential standards. You may use single-ended standards too, like LVCMOS25. In this case, _P and _N traces will have crosstalk between them. Stronger coupling benefits differential noise rejection, but causes higher crosstalk between single-ended traces. In single-ended applications, depending on signal rise times, this might cause issues. In such cases use either _P or _N side for the useful signal and drive the other side with constant 0 or 1. It wastes pins, but helps with crosstalk. As always, check the schematic, reference manual and SelectIO user guide. The latter for verifying different I/O standard compatibility in the same bank, supply and termination requirements.
  15. Look for Vivado_init.tcl in: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug835-vivado-tcl-commands.pdf https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug895-vivado-system-level-design-entry.pdf
  16. I just opened a project originally created in 2016.4 in Vivado 2017.4, updated all the IP, edited dvi2rgb by adding whitespace to one of the files, repackaged the IP, upgraded the IP in block design and successfully built it. Functional test passes too. Editing the IP the second time still does not show the xit file you mentioned. Are you getting error messages related to board definition files? I needed to created a Vivado_init.tcl with path to our vivado-boards repo so that I wouldn't get errors related to board interfaces.
  17. elodg

    HDMI Customization

    DVI/HDMI is not easy. Which is the reason why we provide both an input and an output ip over at https://github.com/Digilent/vivado-library . You may re-use them without the need to understand the exact implementation. Or you can look at the source files, since we do provide the VHDL. A user guide is also available at the same location. To understand the protocol itself, read the specs. For example: http://www.cs.unc.edu/~stc/FAQs/Video/dvi_spec-V1_0.pdf I do admit that our DVI IPs are missing testbenches, so I cannot help with simulations. However, dvi2rgb has an ILA debug module option that can help you to look at signals.
  18. What makes you think the culprit is RefClk? I will add a debugging section to the documentation to make recognizing the error message easier.
  19. Hello @tbrowning, Error 1 is due to the fact that each dvi2rgb instantiates its own IDELAYCTRL, which really aren't that many of in the FPGA. The solution would be what Xilinx IP do, having an option for instantiating shared logic externally. Or having an IP customization option for instantiating IDELAYCTRL. If you do implement that, please contribute back. Error 2 must be some new Vivado sh!@$$&#&$. I have not seen this in earlier versions. Maybe try creating a new IP and importing sources.
  20. Translation of the error message: The MMCM primitive in dvi2rgb is getting a 165MHz input clock, which it multiplies by 10 and divides by 1, resulting 1650 MHz internal VCO frequency. This is outside its operating range as per the Zynq datasheet. The problem is that the DVI implementation needs a serialization clock five times the frequency of the input clock. There are several sets of multiplier and divider values possible to achieve this, but not all result in a valid VCO frequency and no single set covers the whole range of pixel frequencies (video resolutions). Adjust the IP settings to higher expected resolutions: >120 MHz (1080p). BTW all this is already described in the dvi2rgb user guide.
  21. For sure they are not pin compatible, but adhere to the common VITA.57 spec. You will need to change the XDC location constraints, but otherwise the same features are available in the G2 FMC connector as on the Xilinx ones. If anything the Digilent board has more pins wired, the G2 FMC connector is a fully-bonded High Pin-Count connector. The only place where you can wire into the GTX transceivers are shown on pg 14 of the schematic: DisplayPort and FMC DPx pins. DisplayPort connectors have not been tested with >5.4 Gbps, nor they are certified for those rates. This leaves you with the option of designing an FMC mezzanine card for yourself that have the ADC, DAC and SFP+ cage on it. For I2C you may use any of the User I/O pins of the FMC: LAx, HAx... Or even Pmods. Pay attention to I/O voltages.
  22. @aytli, There are two behaviors you are questioning: initialization upon reset and caching. Initialization has both a hardware and a software component to it. By RAM I assume you are referring to DDR3. The content of DDR3 memories are undefined after a power-down event. It could be random data or Mona Lisa, with the latter having a negligible chance. The software component in this case is governed by the specifications of the C language referring to initialization of variables. For example: If an object that has automatic storage duration is not initialized explicitly, its value is indeterminate. If an object that has static storage duration is not initialized explicitly , then: —if it's as pointer type, it is initialized to a null pointer; —if it's an arithmetic type, it is initialized to (positive or unsigned) zero; —if it is an aggregate, every member is initialized (recursively) according to these rules; —if it is a union, the first named member is initialized (recursively) according to these rules. Your digits variable has static storage duration so it is initialized to zero by the loader or the C runtime. According to your debugger this was implemented. Your issues must stem from a caching behavior. You have two masters accessing the memory: processor and video DMA. The processor goes through a D-cache, while the DMA has direct access. This means that the two master's view of the memory is not the same: the DMA is not seeing what you are writing in software, because data is held in the cache instead of written out to memory. Do a D-cache flush after writing the frame buffer from software to commit the new values to the memory. The header xil_cache.h has a Xil_DCacheFlush function declared in it.
  23. @Weevil, The error is due to an invalid connection. PXL_CLK_5X_O uses a BUFIO internally that cannot be routed to an external pin, which is what you are trying to achieve. To make it work, leave it unconnected and use PXL_CLK_O for internally clocking your DDS Compiler instance. These are particularities of the axi_dynclk IP due to it being meant for video applications. If you cannot make it work, see other options below. For dynamic clock generation, you have two IP options: Xilinx Clocking Wizard with AXI-Lite interface or the Digilent axi_dynclk. Advantages of Clocking Wizard: clock buffer options more suitable for non-video applications, documentation Advantages of axi_dynclk: clock buffer options (BUFIO, BUFR) suitable for video applications, driver with VCO parameter calculation. The Digilent axi_dynclk in the master branch of vivado-library does not have a standalone driver nor documentation. It does have a linux driver though. See issue https://github.com/Digilent/vivado-library/issues/14 However, there is a new version of axi_dynclk with a standalone driver on a different branch: https://github.com/Digilent/vivado-library/tree/feature/axi_dynclk_driver
  24. Indeed, the project included in the workspace does not work. But if you create a new "lwip echo server" example project in SDK along with a new BSP, that works. Make sure any software firewall is off or allows ping packets.
  25. See what the terminal says on the USB/UART port of the Anvyl. Does the lwip server bind successfully to the IP?