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Everything posted by elodg

  1. I sent a PM to @manboy and @Paul Chang on this matter.
  2. The prototypes have been verified, and we got entangled in support for 2020.1. Sorry, I do not have a better timeline.
  3. It could be that 25MHz is some propagated value but starting with 100MHz MIPI clock from MIPI_DPHY_Receiver_ooc.xdc (out-of-context synthesis) and 84MHz is calculated from a MIPI clock constrained in the top-level design. I think this is missing constraints bug in the demo projects. We will look into it.
  4. So cable drivers must be installed if you can program the FPGA. As to why you cannot run Hello world, check the logs for clues on whether elf download succeeds and could even try debug to see where the processor is stuck at. SDK terminal show a crash of some sort.
  5. Did you forget to install the cable drivers perhaps? https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug973-vivado-release-notes-install-license.pdf#G5.401934
  6. I don't think what you are trying to do is possible. Library xfopencv, Xilinx's OpenCV implementation for HLS, much like the original one assumes there is an OS.
  7. That does not sound right. All the functions the PMCU serves is described in the reference manual, which include important ones like VADJ control or thermal cooling control. If LD21 does not blink on power-up the wake-up pattern, the PMCU is either missing its firmware or is otherwise damaged. If there is still a bootloader in it, we can try a firmware upgrade through USB-UART, not J38. A colleague of mine will PM you with the instructions. If firmware upgrade fails we will do an RMA. Is there a change the PMCU has been erased using an programming cable through J38?
  8. Frustratingly, I could never find the equation that worked consistently across resolutions for the HS values the camera uses. The sensor datasheet is not exactly verbose on the matter. Xilinx MIPI DPHY IP support is expected together with UltraScale+ support in a month or so. You can try setting a large value in the sensor for HS_ZERO, and try increasing HS_SETTLE in D-PHY Rx until it works.
  9. We are looking at the build issues you are having to see if we can reproduce them. The issue with two cameras not working is most probably not related, however. Mechanical durability for mating is at least 30 cycles. Re-check cabling, maybe swap Pcams between ports. Also check if there are any messages on the console related to the initialization sequence. There might be errors reported for the non-working cameras.
  10. You are on the right track. The settings that control the timing of the low-power high-speed transition need to match between the transmitter and receiver. It is easier if you scope it, triggering on an LP-10 state and measuring the time it takes for the sensor to switch to high-speed. The following registers control the camera timing: //MIPI timing // [5]=0 T_LPX global timing select=auto pclk2x {0x4805, 0x10},//Default=0x10 //T_HS_ZERO = MIN HS ZERO + T_UI*MIN HS ZERO_UI //MIN HS ZERO H (ns) {0x4818, 0x00},//Default=0x00 //MIN HS ZERO L (ns) {0x4819, 0xFF},//Default=0x96 //MIN HS ZERO_UI {0x482A, 0x05},//Default=0x05 //T_HS_PREPARE = MIN HS PREPARE + T_UI*MIN HS PREPARE_UI //MIN HS PREPARE H (ns) {0x4826, 0x00},//Default=0x00 //MIN HS PREPARE L (ns) {0x4827, 0x32},//Default=0x32 //MIN HS PREPARE_UI {0x4831, 0x04},//Default=0x04 We will get to publishing a Xilinx MIPI IP demo project eventually.
  11. elodg

    Pcam Visible Border Line

    You can try editing the AXI_BayerToRGB or replacing it with Xilinx's demosaic IP. You can try interpolation with duplicated margin, for example. You are on your own.
  12. elodg

    Pcam Visible Border Line

  13. elodg

    cmod S7 zyboZ7 connection

    UART over Pmod.
  14. elodg

    cmod S7 zyboZ7 connection

    Sending it to a PC first then to the ZyboZ7 through two USB-UART connections.
  15. See Supported Devices in https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug973-vivado-release-notes-install-license.pdf. Pre-7 series devices, like CoolRunner-II are not supported in Vivado.
  16. elodg

    cmod S7 zyboZ7 connection

    Sure you can, but probably not worth the hassle. You need to implement and inter-board protocol on both ends and use the Pmod as a physical medium. Probably UART or SPI, to keep things simple. Then on the Zybo Z7 implement a SPI to AXI adapter to get tot the memory.
  17. DDR2/DDR3 designs work fine without driver impedance control, even in non-point-to-point topologies. Maybe Xilinx considered that receiver termination is enough to cover all use cases and the board designer should provide that. In our point-to-point topology, we could achieve compliance with a much simpler driver impedance adaptation. We do not generally provide gerbers. If you think your use case is legitimate, contact us at https://store.digilentinc.com/further-assistance/ and we might be able to provide them under NDA.
  18. What you are saying is a tad too big of a leap. All I can say is that 22-ohm series resistor added to the driving impedance met the design requirements.
  19. Each design is validated independently. Any tactic can be employed as long as the DDR3 specifications are met. Ideally the line is terminated at both ends, and drive impedance matches line impedance and input impedance. Some designs only employ parallel receiver termination, others only series drive impedance matching. The Cora Z7 is the latter, the Xilinx dev kit is probably the former.
  20. From ug585 pg. 310: For DDR3 DCI calibrates the termination impedance and not the driver impedance. Series termination resistors is a form of drive impedance adaptation.
  21. Quoting from https://reference.digilentinc.com/reference/programmable-logic/anvyl/reference-manual#flash_memory: What makes you think it is only for FPGA configuration? Instantiate the AXI Quad SPI IP and map it to the pins called out in the RM and schematic.
  22. One can get lost pretty easily as the learning curve is steep and the same goes for us too. We are hard at work getting 2020.1 support published for G-ZU and we are seeing our fair share of issues. We do not have a BSP published, but the https://github.com/Digilent/Genesys-ZU-OOB-os repo should be just as good of a starting point. For now it is only for 2019.1 but we successfully created Ubuntu rootfs for internal use with it. It is our sole supported version at the moment.
  23. The best way would be a pull request on github, provided that the changes you did for FreeRTOS do not break standalone compatibility.
  24. elodg

    HDMI directly into FPGA

    Carefully evaluate your system requirements (resolution, link rate) and do board-level simulation on the TMDS signals. FPGA user I/O pins have considerable capacitance and might close your signal eye too much. Buffers like the TMDS141 help with decoupling cable segment from the PCB, making longer PCB traces possible. Our development boards are not HDMI-certified, but buffers might make passing electrical certification easier.
  25. @hendog82, give us some info on your setup. What Petalinux version are you using and what kernel and apps recipes you configured for ptp?