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elodg last won the day on April 22

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  1. I have never tried this app note. I will, when I get the chance, but no promises.
  2. https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1 This will install board definition files for the ZYBO. Then, in your project settings you can choose the board and not the Xilinx part. Finally, instantiating the PS IP and running block automation will give you the option to apply board preset to the processor. In your case, in an existing project it is probably better to import a preset to the Zynq Processing system only. I don't know why we haven't published this before, but I added it to our ZYBO repo: https://github.com/Digilent/ZYBO/tree/master/Resources/Preset Just go to Presets -> Apply Configuration and choose the tcl file from above.
  3. Read the GPIO section of ug585. The XGpioPs driver maps MIO and EMIO into different GPIO banks and uses sequential designators mixing the two. You most probably should not be reading bank 0 or pin 0.
  4. The easiest way is getting that version, running the scripts to generate the hardware project and then opening it in your new version, where an upgrade will be performed. The hard route is going into build_bd_design.tcl and manually editing it to deactivate the version warning and modify all IP versions to their current version in "create_bd_cell" commands. Then trial-and-error until the project gets generated without errors. Depending on the IP changelogs there might be interface differences, but those are rare.
  5. All the example projects on our Github page that use the PL-to-PS interrupt: https://github.com/search?utf8=✓&q=org%3ADigilent+IRQ_F2P++extension%3Atcl&type=Code&ref=advsearch&l=&l= In 2016.4 at least I am getting the correct defines in xparameters.h: #define XPAR_FABRIC_XADC_WIZ_0_IP2INTC_IRPT_INTR 61 #define XPAR_FABRIC_AXI_DMA_0_MM2S_INTROUT_INTR 62
  6. The examples assume that you are using either axi_intc (Microblaze) or scugic (Zynq). You are mixing the two in your project only you know why. Theoretically it should work, but there are two interrupt controllers to initialize and setup handlers for. Scugic needs to enable the first F2P interrupt ID and set its handler to XIntc_InterruptHandler (or something like that). XIntc needs to enable the peripheral interrupts and set the appropriate handlers for each. Add probes to interrupt lines and check with the logic analyzer to confirm the propagation of the interrupt signals. Add software breakpoints to handlers to confirm that the proper ones are called. Honestly, if the type and polarity of the peripheral interrupts are compatible with Scugic, removing axi_intc from the design is probably easier. Then, all interrupt-based examples should work.
  7. First, open the synthesized design netlist in the IP project and see if anything got optimized due to bad HDL. Then, do the same in the project that instantiates your IP and ties the AXI bus to a master. Watch for warnings related to nonexistent objects, inputs hard-wired to constants or unused signals.
  8. For sure you will need to apply the correct preset to the board. Input clock frequency, DDR3 parameters and MIO mapping most probably differ between the two boards. After you apply the Zybo preset check the differences between the two preset, stuff like which UART controller should be used for stdout. Also, you were saying it does not show anything after booting from SD. Define FSBL_DEBUG and confirm that it actually boots your application. Also try launching over JTAG from SDK.
  9. Jumpers J1 should be left on all the time. If the DA/DB pins of the mux show a different voltage than the A-dependent SxA/SxB pins, the mux is broken and you can try claiming warranty. If the mux works fine and the XADC measures a negative differential voltage with floating inputs, but none of the pins is negative w.r.t. GND, it is working as expected. You can avoid floating inputs by doing a touch presence measurement first. Glad you got it working.
  10. Just to be clear, you are digitally driving '1' to XD+ and '0' to XD-, resulting in a drive of 2.5V. The rest should be HiZ. Just for the kick of it, using a voltmeter measure between XS+ and XS-. This is the voltage across the X panel put in series between the 1K and 150ohm resistors on-board forming a resistive divider. This is independent of touch and is caused by the characteristic resistance of the panel. To measure actual touch coordinate, you need to measure between YS+ and XS-. XS- is a point in the resistive divider, close to 0V and YS+ is floating, if there is no touch. If there is touch, YS+ is too inserted in this resistive divider and you should measure a voltage that is between 0V and 1V. Measuring floating inputs should not result in stable negative measurements. Read http://www.ti.com/lit/an/slaa384a/slaa384a.pdf again and draw a schematic for better understanding.
  11. According to ug190 pg. 297 a LVPECL-compliant transmitter needs a three-resistor output termination circuit that is not present on the Genesys. A further requirement from pg. 299 is the 2.5V bank supply voltage, which is available in bank 3, 12 and selectable on 11, 13. Banks 11 and 13 are the ones wired to the VHDCI connectors and your best bet is creating a custom board or using something like http://store.digilentinc.com/all-products/modules-add-on-boards/vmod-vhdci-expansion-modules/ to get your signal out of the board and add the termination resistor. It is not ideal, because it won't be near-end anymore, but it might work.
  12. Well, "failed timing" is like saying the sky is blue. You got to tell us more if you want help with that. Google Xilinx timing closure for more info. Here is one link that is a good starting point: https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0006-vivado-design-analysis-and-timing-closure-hub.html
  13. Bank 33 is a 1.5V-powered bank. Make sure sysclk is input, because only LVDS inputs without internal termination are compatible with any bank supply voltage. For more information, see ug471 from Xilinx.
  14. Hi @BeamPower, This might be relevant: https://smallshire.org.uk/sufficientlysmall/2013/10/31/arduino-avr-gcc-eclipse-and-windows-8-1/ Open the Xilinx Software Command Line Tool for your SDK version from the Start menu. Cd into your SDK project's Debug or Release folder and try running make clean and make from there. See if it errors out. The link above describes a similar issue with the Windows build of GNU make. In any case, this is a Xilinx tool issue.
  15. Hello @Lakshmi morla, The PHY address is in the ref manual: https://reference.digilentinc.com/reference/programmable-logic/genesys-2/reference-manual#ethernet_phy The I/O standard compatibility errors are due to incorrect LOC constraints. Figure 7 in our reference manual shows incorrect locations for Ethernet pins. Please use the XDC file instead that has all the pins and their correct locations. Depending on your application you might need to change the I/O standards for Pmod and FMC signals. Other on-board peripherals should have the correct I/O standard specified and are wired to FPGA banks with compatibility in mind.