elodg

Digilent Staff
  • Content count

    55
  • Joined

  • Last visited

  • Days Won

    6

elodg last won the day on August 7

elodg had the most liked content!

About elodg

  • Rank
    Frequent Visitor

Recent Profile Visitors

763 profile views
  1. @dummyC, The Nexys3 came with an older version of the firmware that did not support flash drives announcing high power requirement. Please try with an older pen drive, one that does not require more than 100mA of current. Device Manager in Windows 7 shows this info for the root hub the pen drive is connected to. There is an update for the Nexys3 firmware, but it needs to be loaded from an already working pen drive. This update should extend the range of supported pen drives. I will send the update in a PM.
  2. @pawel.pawelec Try the attached core version, see if it works. I believe GoPro requires CEA extension block in the EDID for it to work. dvi2rgb_v1_6.zip
  3. It is impossible to support all the I/O standards with the recommended terminations schemes on a generic connector. Pmod is for LVCMOS33 mainly. XADC Pmod is for analog differential mainly. Provided that you are willing to give up warranty and do some hacking, you can try to make it work. For LVDS output you will need VCCO=2.5V which the Nexys Video is capable of. The other end will need the standard 100ohm differential termination. If you leave the two 100 ohm series resistors there, the voltage swing will be the third of the nominal value. It might be enough if the receiver has wide operating range. Short the resistors for larger swing. For inputs, VCCO=2.5V will give you internal terminations. The series resistors will have the same effect as above. If you have only 3.3V available, you will have to load a parallel termination resistor. For the Pmod XADC on the Nexys Video you can do that on the capacitor footprint in the anti-alias filter. All the above concerns voltage levels only. Impedance mismatches will cause considerable signal degradation if the signal edges are steep enough. Other than slowing down the signal, there is nothing more you can do. Safe hacking!
  4. Make sure the whole DDC bus is connected to the external port directly. The I/O buffer should be automatically inferred and the only external ports you should see are ddc_scl_io, ddc_sda_io. I edited the table in the reference manual to make it clearer that the pins are grouped by connector. You will need either the Sink or the Source column. Regarding the SDK error messages, try re-creating the hardware platform by importing the hand-off file, and the BSP by creating a new one and overwriting the mss file with the old one.
  5. I could not yet find the time to try those application notes. Digilent does not provide bare-metal demos for dual-core operation. I am wondering whether the Xilinx forum would not be more appropriate.
  6. I will refrain from the socio-political aspects of this question. Purely from the technical perspective, I am thinking replacing that manual labour step with cameras and image recognition. I cannot think of anything else that is easier to implement and close to impossible to cheat.
  7. How is this question different than ? Possible duplicate.
  8. Looking at the block design and the interrupt handlers here is what is happening in the example design: when an HDMI clock is detected, the GPIO interrupt is triggered and gets handled by GpioIsr. This in turn enables the vtc (Video Timing Controller) interrupt. If a known resolution is detected on the timing signals, the vtc interrupt is triggered and gets handled by VtcIsr. This reads in the detected timing information (videoPtr->timing) and calls VideoStart. You either need to tie all camera sync signals (not just v_sync) to vtc, if the camera outputs at a VESA standard timing, or replace the timing detection mechanism altogether. A quick and easy way is to hard-code the timing information, since it is you who is configuring the camera to a set resolution. In this case, remove the interrupts altogether and call VideoStart when the camera is transmitting. Mismatch in number of pixels and lines between the camera and VDMA might cause errors or lock-up. Use Vivado to insert logic analyzer probes and follow the video stream as it flows from the camera to the VDMA. Since the pattern is shown I expect the output stream (from the VDMA to the VGA) to be working.
  9. I have never tried this app note. I will, when I get the chance, but no promises.
  10. https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1 This will install board definition files for the ZYBO. Then, in your project settings you can choose the board and not the Xilinx part. Finally, instantiating the PS IP and running block automation will give you the option to apply board preset to the processor. In your case, in an existing project it is probably better to import a preset to the Zynq Processing system only. I don't know why we haven't published this before, but I added it to our ZYBO repo: https://github.com/Digilent/ZYBO/tree/master/Resources/Preset Just go to Presets -> Apply Configuration and choose the tcl file from above.
  11. Read the GPIO section of ug585. The XGpioPs driver maps MIO and EMIO into different GPIO banks and uses sequential designators mixing the two. You most probably should not be reading bank 0 or pin 0.
  12. The easiest way is getting that version, running the scripts to generate the hardware project and then opening it in your new version, where an upgrade will be performed. The hard route is going into build_bd_design.tcl and manually editing it to deactivate the version warning and modify all IP versions to their current version in "create_bd_cell" commands. Then trial-and-error until the project gets generated without errors. Depending on the IP changelogs there might be interface differences, but those are rare.
  13. All the example projects on our Github page that use the PL-to-PS interrupt: https://github.com/search?utf8=✓&q=org%3ADigilent+IRQ_F2P++extension%3Atcl&type=Code&ref=advsearch&l=&l= In 2016.4 at least I am getting the correct defines in xparameters.h: #define XPAR_FABRIC_XADC_WIZ_0_IP2INTC_IRPT_INTR 61 #define XPAR_FABRIC_AXI_DMA_0_MM2S_INTROUT_INTR 62
  14. The examples assume that you are using either axi_intc (Microblaze) or scugic (Zynq). You are mixing the two in your project only you know why. Theoretically it should work, but there are two interrupt controllers to initialize and setup handlers for. Scugic needs to enable the first F2P interrupt ID and set its handler to XIntc_InterruptHandler (or something like that). XIntc needs to enable the peripheral interrupts and set the appropriate handlers for each. Add probes to interrupt lines and check with the logic analyzer to confirm the propagation of the interrupt signals. Add software breakpoints to handlers to confirm that the proper ones are called. Honestly, if the type and polarity of the peripheral interrupts are compatible with Scugic, removing axi_intc from the design is probably easier. Then, all interrupt-based examples should work.
  15. First, open the synthesized design netlist in the IP project and see if anything got optimized due to bad HDL. Then, do the same in the project that instantiates your IP and ties the AXI bus to a master. Watch for warnings related to nonexistent objects, inputs hard-wired to constants or unused signals.