elodg

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About elodg

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  1. I added the maximum theoretical data rates for SATA (600MB/s) and PCIe (500MB/s) to the reference manual. I do not have benchmarks at the moment, but I recommend mSATA. Good mSATA modules should bench at least 200MB/s read speed.
  2. The Genesys ZU was validated with a 16GB 2Rx8 ECC module (SQR-SD4I16G2K4SEBB). The PS DDR4 controller is limited to 34GB, so theoretically a sixteen-component 2Rx8 module (32GB) would also work. Keep in mind that dual-rank components max out at a one step lower data rate (1600-3EG; 1866-5EV).
  3. The board in question will be replaced. Thanks for bringing it to our attention!
  4. While looking at this I found an issue in our Genesys 2 reference manual which was not detailing the PHY-internal delays in accordance with the schematic. I hope the revised section makes it clear now: https://reference.digilentinc.com/reference/programmable-logic/genesys-2/reference-manual#ethernet_phy. You have the RXDLY and TXDLY configuration straps wrong. Also double-check what delays does the MAC in your design introduce. The traces are matched to +-10ps. Package delays would need to be added, but considering a total +-50ps mismatch is conservative enough and will not be hard for th
  5. I believe those parameters are just for generating the example design, of which there is only one for that specific Xilinx TRD system.
  6. The USB port on the Nexys A7 only implements embedded host functionality. If you wish to communicate with a PC, the simplest is UART, which appears as a Virtual COM port on the PC.
  7. elodg

    DVI2RGB TB

    DVI is a source-synchronous digital interface where the clock sent on a dedicated lane separate from data is not directly used for sampling. DVI specifications allow for an inter-pair skew at the transmitter (!) of 20% of the pixel clock. At the receiver this increases to 60%. For practical purposes, phase of data wrt. to SerialClk and PixelClk do not matter at all. It is the responsibility of the receiver to reconstruct the SerialClk from the TMDS clock, adjust the phases of each data lane independently until it locks onto the middle of the eye, and find the pixel word boundaries in the strea
  8. BTW, XilIsf is deprecated: https://www.xilinx.com/support/answers/73329.html You could (carefully) add ILA to the QSPI interface and decode the commands. Haven't looked at the code, but check clock frequency and write enable command. Try the regular READ and Page Program commands.
  9. The bus is sampled every 30us, which is the time it takes to detect a Host Inhibit Communication condition. However, the protocol state machine, data buffering and command processing shares MCU time with other tasks, like USB. Therefore, it takes a variable amount of time after the Host Inhibit Communication is detected to detect Host Request to Send and kick off clock generation. From https://web.archive.org/web/20060901070855/http://www.computer-engineering.org/ps2protocol/: "The device should check for this state at intervals not to exceed 10 milliseconds." "Referring to Figu
  10. Trouble with homework, @tommytml? The FPGA is flexible enough to allow for a different clock input. The on-board (shared) oscillator produces a single-ended 12 MHz LVCMOS33 signal wired to pin L17 as described here: https://reference.digilentinc.com/reference/programmable-logic/cmod-a7/reference-manual#oscillatorsclocks However, you are free to assign the clock port in your design to a different pin on the DIP connector. Find the right pin in the schematic: https://reference.digilentinc.com/_media/reference/programmable-logic/cmod-a7/cmod_a7_sch.pdf Xilinx documentation will tel
  11. The part number in the Zybo schematic points to the ADI part with factory defaults. Only VCC3V3 is monitored, but it is also the last one in the daisy-chain sequence. So all power rails are monitored indirectly.
  12. The name of the IP might be deceptive. RGB output is not guaranteed. The IP's EDID declares preferred resolutions and color formats through the DDC bus, but it is up to the connected Source to determine compatibility and transmit the right formats. The DVI/HDMI/TMDS encoding/decoding is transparent wrt the picture format. Use ILA on the rgb interface and the included debug module to see what is going on.
  13. The most up-to-date files are there in the location you pointed out. There aren't many board interfaces present, but the most important is the MPSoC preset, which is there.
  14. There is nothing blatantly wrong. Check XDC, sys_clk frequency and monitor source settings. You can also add ILA cores to your design to make sure vtc is working.
  15. From the repo readme: https://reference.digilentinc.com/reference/programmable-logic/documents/git#vivado_hw_projects