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elodg last won the day on August 27 2018

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About elodg

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  1. elodg

    Pcam 5C camera module interfacing

    Hello @Suavek, I gave our SDSoC reVISION platform a try, because it is Linux-based and supports Pcam 5C. Booting the platform I get the following: root@Zybo-Z7-20:~# v4l2-ctl -d /dev/video0 --verbose --list-formats-ext VIDIOC_QUERYCAP: ok ioctl: VIDIOC_ENUM_FMT Index : 0 Type : Video Capture Multiplanar Pixel Format: 'YUYV' Name : YUYV 4:2:2 Index : 1 Type : Video Capture Multiplanar Pixel Format: 'UYVY' Name : UYVY 4:2:2 Index : 2 Type : Video Capture Multiplanar Pixel Format: 'NM16' Name : Y/CbCr 4:2:2 (N-C) Index : 3 Type : Video Capture Multiplanar Pixel Format: 'NV16' Name : Y/CbCr 4:2:2 Looking at the Petalinux BSP project that is used in our SDSoC reVISION platform too, v4l2 support for the Pcam5C is coming from Xilinx Petalinux recipes for the MIPI CSI2 Rx Subsystem and Video Processing Subsystem IPs: https://github.com/Digilent/Petalinux-Zybo-Z7-20/commit/59be69aa92699cc26083c2ece87c28e2991151b3 Unfortunately, both IPs require a license (either separate or included in the SDSoC license), if you are re-creating the hardware platform, but you can use it as reference. Build a new Petalinux project using our BSP and compare devicetrees.
  2. elodg

    Genesys2 Display Port

    @MateoConLechuga, what I meant is that the OOB demo that the board is programmed with in factory correctly drives DisplayPort. Indeed, none of the source files we provide on Github work. Thanks for publishing your project.
  3. elodg

    Genesys2 Display Port

    The out-of-box demo in the flash memory drives the DisplayPort out and you should see it working. The source files for the project are here, where Jon linked to. The issue with the DP IP in the demo was that it requires a license to generate a bitstream, so it was removed and re-published here. I am glad you made it work, I know the feeling of satisfaction when that happens. I am eager to find out what was actually wrong with what you were trying.
  4. Hello Blake, Sincere apologies for the process taking so long. I will have to ask for your patience again. @BogdanVanca will send you a test project for the Zedboard + FMC-HDMI combo and instructions on how to execute the tests that are also used in manufacturing. I have to commend you for the clear description of the problem and all the debug work you already did. The message quoted above is expected for the first run on a new FMC-HDMI. It is unrelated to your issue. Let's wait for the test project and see the results before we go further.
  5. elodg

    Nexys Video "Feet"

    https://www.fastenal.com/products/details/0146057 https://www.fastenal.com/products/details/28783
  6. elodg

    ZedBoard XADC Header Dedicated Inputs

    @mehmetdemirtas89, The picture only shows that you can connect an input signal that has a DC component of maximum 0.5V and an AC component of maximum 0.5V. So the +-0.5V AC can have and offset between 0-0.5V. This is a signal between -0.5V and +0.5V or between 0V and 1V at the extremes.
  7. elodg

    On and off-chip connections with EMIO GPIO

    In block design, this is the way to do it. Other than writing it in VHDL and adding it as module.
  8. elodg

    Facing error in the rgb2dvi IP

    The error message complains about the internal frequency of the MMCM in rgb2dvi being too high. There are two things that influence the error message: the input clock frequency, and the parameters of the clock primitive. The input clock frequency is propagated from dvi2rgb and is originally coming from the TMDS_rx_i_clk_p port. The parameters of the clock primitive are exposed in the rgb2dvi IP wizard as the expected resolution/clock frequency. Your project seems to have the latter set to expect a low resolution/frequency, hence the 15x multiplication factor. However the input clock is timed for the highest DVI frequency possible at 165MHz (6.06ns). In a synthesized design you can execute the write_xdc command to dump all constraints to a file. Then look for the erroneous clock definition to find where it is coming from.
  9. There you go: https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/reference-manual#hardware_errata
  10. @thobie, the bare-metal purchase option for the Zybo was done to enable a lower price point for those who do not require the accessories. For the rest of our customers, adding the Accessory Kit is recommended during the purchase process. You are not the first and the last to complain about version compatibility. It is economically unfeasible for us to update all support projects, IP and support packages provided for free four times per year for each Vivado version. Instead we made a commitment to consider the last Vivado release in each year stable and do a once-a-year update cycle. In that regard, 2017.4 is the version we are upgrading projects to. There is a question whether OOB designs should be updated at all, or kept at the version which generated the binary image shipped with the board. The board presets are not versioned for Vivado (no version-specific releases in our git repo), because these should be forward-compatible with Vivado versions. The critical warning itself related to CK-to-DQS delays being negative appears starting with 2017.4. The negative values are due to CK trace being shorter than any of the four DQS traces. In the early days of Zynq board design negative values where listed as sub-optimal, but not erroneous. Tree topology instead of fly-by was also among the routing recommendations for DDR3 layouts. So the Zybo was designed with this sub-optimal layout due to space constraints. During Write Leveling calibration, 0 is used as an initial value instead of the negative preset delays. After calibration, if the skew is still too low, the clock is inverted. See ug585 pg 316 for more details. All Zybos shipped to customers are functionally tested and pass the DDR3 calibration process. Xilinx recommendations changed in the mean time, both in terms of routing topology and delay values. A trace of this can be found here: https://www.xilinx.com/support/answers/53039.html. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted. Since these delays are board-dependent, we would need to re-design the board to make the delay positive. This is impossible with the current form-factor. Another option would be modifying the board preset file and forcing a zero value instead of the actual delay. The tools seem to be using zero anyway for calibration. This will have to be thoroughly verified first.
  11. elodg

    MIPI to Digilent board, transfer rate, which boards work?

    MIPI CSI-2 cameras use MIPI D-PHY for the physical transport layer. The D-PHY I/O standard is only supported by UltraScale+ I/O pins. Any other architecture needs some form of adaptation. The compliant solution is the Meticom D-PHY-LVDS translator. A compatible solution with a passive termination network is described in https://www.xilinx.com/support/documentation/application_notes/xapp894-d-phy-solutions.pdf The compatible solution is in use on our Zybo-Z7 board's Pcam connector, which allows connecting one Pcam 5C camera module. It works up to the maximum data rate supported by the Pcam 5C, 672Mbps per lane, or 1344Mbps total. Your data rate is a bit high. Check the per lane data rate, which will tell you whether the passive termination suffices or your will need an active level translator. In any case, getting those high data rates into the FPGA requires high-speed connectors, like the purpose-made Pcam or the generic FMC connector. FPGA datasheets will tell you the maximum data rate supported by LVDS transmitter/receiver depending on speed grades. Some of our upcoming products will feature more than one Pcam connector. Check back for updates!
  12. HDMI_TX_HPD is input, HDMI_RX_HPD is output. See https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/reference-manual#hdmi Leave HDMI_TX_HPD unconnected, if not used. Why don't you look at a demo we have on our Github: https://github.com/Digilent/Zybo-Z7-10-HDMI? Debug your design by tying signals to LEDs or ILA modules. The flow is the following: Sink (Zybo Z7) asserts Hot-Plug Detect -> confirm that HDMI_RX_HPD is tied high. Source (whatever you have connected) queries the capabilities over DDC -> confirm that Digilent DVI appears as a secondary monitor on a PC for example. Source begins transmitting video -> confirm that the Source actually enables the secondary monitor and drives a compatible resolution. Sink locks onto the signal -> confirm that clk_wiz is locked and dvi2rgb/aPixelClkLckd goes high. Video is decoded -> confirm dvi2rgb/VSync, HSync and VDE are toggling. Video appears on output -> confirm hsync and vsync are correctly timed for the expected resolution.
  13. elodg

    Nexys 4 DDR with a new DDR2 chip

    Check your internet connection, it works for me.
  14. elodg

    NexysVideo PHY-MAC routed delay path

    It was left off from the capture, but those values are trace lengths in mm. C23 is reserved there for EMC purposes, it has nothing to do with the delays you are looking for.
  15. elodg

    NexysVideo PHY-MAC routed delay path

    The skew demanded by the RGMII specs between clock and data groups has not been implemented on the PCB. See the trace lengths below (unit mm) for delay matching inside the signal groups. This implies that the skew must be implemented in the MAC and/or PHY. The PHY has internal delays that are configurable by pull resistors on pins 32 and 16: R88/83 and R72/79. The board is shipping with no PHY delays enabled as written in the reference manual: You may change these on your board. The reason for no delay matching by default is because of the flexibility in MAC implementation in the FPGA. Check the exact MAC IP for delay matching. If it is not readily configurable, enable it in the PHY instead.