elodg

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About elodg

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  1. A quick note here. The source files that need editing are part of a library (https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841939/xilisf) compiled into a bsp/domain. By navigating to the source files in SDK/Vitis, the local copy of the library's source files are opened. Any modification is done on this local copy and build into the static library (and application) upon build. However, when the source files of the bsp/domain are re-generated (context menu, Regenerate BSP sources), the changes are overwritten from the originals in the Xilinx install directory. Take care this does not h
  2. 1. Table 8 from the datasheet shows how pins HSx_P and HSx_N can be swapped by the level translator: http://www.meticom.com/resources/Datasheets/MC20901-V1_08.pdf. It has been done for easier routing in layout. 2. LPx_LANE1 and LPx_CLK and uni-directional because the MC20901 can only do low-power reverse communication on either channel A or E, but only on a single channel. This is a transmission mode part of the MIPI D-PHY spec. The decision was made to make LANE0 the one supporting this mode. This is described in https://reference.digilentinc.com/reference/add-ons/fmc-pcam-adapter/refere
  3. Is a known issue in our D-PHY IP. If you are getting nothing on the terminal I suspect you messed up something in the Vivado project while porting to 7010. I do not want to sidetrack you, but you could try the latest version of the project (2020.1), which has a 7010 port too: https://github.com/Digilent/Zybo-Z7-SW/tree/10/Pcam-5c/next. It uses a new project structure and versioning rules. Read this: https://reference.digilentinc.com/reference/programmable-logic/documents/git#vitis_sw_workspaces
  4. elodg

    PCAM adapter with ZCU102

    This does not make sense. U135 on ZCU102 has FMC_HPC0 on channel 0 FMC_HPC1 on channel 1. By addressing U135 on bus I2C1_SDA/SCL you open the right channel to reach the SDA/SCL bus of the FMC Pcam Adapter. Then you address the IC3 I2C switch on the FMC Pcam Adpter to open a channel to camera A,B,C or D. Depends on how you configure the sensor. If you are using project https://github.com/Digilent/ZedBoard-FMC-Pcam-Adapter-DEMO/blob/174903defd61e3e00feea90fd05c08512dae385f/sdk/appsrc/ZedBoard_FMC_Pcam_Adapter_DEMO/main.cc#L179, then it configures the sensor with OV5640_cfg::mode_t::MODE_
  5. I sent a PM to @manboy and @Paul Chang on this matter.
  6. The prototypes have been verified, and we got entangled in support for 2020.1. Sorry, I do not have a better timeline.
  7. It could be that 25MHz is some propagated value but starting with 100MHz MIPI clock from MIPI_DPHY_Receiver_ooc.xdc (out-of-context synthesis) and 84MHz is calculated from a MIPI clock constrained in the top-level design. I think this is missing constraints bug in the demo projects. We will look into it.
  8. So cable drivers must be installed if you can program the FPGA. As to why you cannot run Hello world, check the logs for clues on whether elf download succeeds and could even try debug to see where the processor is stuck at. SDK terminal show a crash of some sort.
  9. Did you forget to install the cable drivers perhaps? https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug973-vivado-release-notes-install-license.pdf#G5.401934
  10. I don't think what you are trying to do is possible. Library xfopencv, Xilinx's OpenCV implementation for HLS, much like the original one assumes there is an OS.
  11. That does not sound right. All the functions the PMCU serves is described in the reference manual, which include important ones like VADJ control or thermal cooling control. If LD21 does not blink on power-up the wake-up pattern, the PMCU is either missing its firmware or is otherwise damaged. If there is still a bootloader in it, we can try a firmware upgrade through USB-UART, not J38. A colleague of mine will PM you with the instructions. If firmware upgrade fails we will do an RMA. Is there a change the PMCU has been erased using an programming cable through J38?
  12. Frustratingly, I could never find the equation that worked consistently across resolutions for the HS values the camera uses. The sensor datasheet is not exactly verbose on the matter. Xilinx MIPI DPHY IP support is expected together with UltraScale+ support in a month or so. You can try setting a large value in the sensor for HS_ZERO, and try increasing HS_SETTLE in D-PHY Rx until it works.
  13. We are looking at the build issues you are having to see if we can reproduce them. The issue with two cameras not working is most probably not related, however. Mechanical durability for mating is at least 30 cycles. Re-check cabling, maybe swap Pcams between ports. Also check if there are any messages on the console related to the initialization sequence. There might be errors reported for the non-working cameras.
  14. You are on the right track. The settings that control the timing of the low-power high-speed transition need to match between the transmitter and receiver. It is easier if you scope it, triggering on an LP-10 state and measuring the time it takes for the sensor to switch to high-speed. The following registers control the camera timing: //MIPI timing // [5]=0 T_LPX global timing select=auto pclk2x {0x4805, 0x10},//Default=0x10 //T_HS_ZERO = MIN HS ZERO + T_UI*MIN HS ZERO_UI //MIN HS ZERO H (ns) {0x4818, 0x00},//Default=0x00 //MIN HS ZERO L (ns) {0x4819, 0xFF},//Default=
  15. elodg

    Pcam Visible Border Line

    You can try editing the AXI_BayerToRGB or replacing it with Xilinx's demosaic IP. You can try interpolation with duplicated margin, for example. You are on your own.