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About elodg

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  1. Yeah, ISE is no good as it does not work on Win 10. It last worked on Win 7, but that is outdated as well. You need to go with Vivado. OPTION#1 Vivado 2021.1 can pull in the board catalog form XilinxBoardStore, which is has the Zedboard defined. Just click Refresh. The XilinxBoardStore lists it under avnet.com as vendor: OPTION#2: You can install our board files using the steps from https://digilent.com/reference/vivado/installing-vivado/2018.2?s[]=vivado&s[]=init&s[]=tcl#installing_digilent_board_files.
  2. We do not support non-Petalinux flows. However, I am attaching the final dts that results from the Petalinux build of https://github.com/Digilent/Genesys-ZU-OS/tree/3eg/oob%2Frelease%2Fv2.1. Do as you please.system-top.dts.pp
  3. There are two separate issues related to flash device support on Xilinx platforms: Vivado support and software support. It seems that you are looking for the former, while this whole thread is about the latter. Vivado support is documented for each version in ug908, Appendix E: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021_1/ug908-vivado-programming-debugging.pdf#_OPENTOPIC_TOC_PROCESSING_d114e38049. It refers to the capability of Vivado hardware manager to be able to erase and program the memory device. There are no steps involved, Xilinx either supports it or not. I adde
  4. I would recommend using Michael's step-by-step guide (which is also in https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start) and editing the files in-place if you are not comfortable with versioning tools and patching sources.
  5. Will update this thread when we have a conclusion.
  6. Current consumption is not limited by the FPGA. Furthermore, thermal dissipation coefficients are board-dependent. Vivado has no way of knowing what the limitations of the board are. The board was designed with a 2.6 A current limit because that is what it can safely dissipate. All the power components are sized accordingly. You should refer to the board reference manual for power supply limitations: https://reference.digilentinc.com/programmable-logic/arty-z7/reference-manual#power_supplies, not the individual datasheet of the on-board regulator. We do not recommend you changing the curr
  7. I am sorry to hear about your troubles. Unfortunately, we only tested (m)SATA with 2019.1 and it looks to me that Xilinx changed the GTR calibration procedure in the FSBL since then. I suggest using 2019.1 with the Genesys-ZU-OOB-os/hw repos, which is the supported version. In the mean time we will investigate how the GTR link training changes affect SATA in 2020.1. May I ask what other issues needed fixing in the devicetree?
  8. FMC modules are inserted in series into the JTAG chain. FMC modules must make sure to insert a device there or loop TDI back to TDO if JTAG is not used. According to the schematic jtag signals go to a header: https://www.xilinx.com/support/documentation/boards_and_kits/xtp078.pdf Just short the TDI and TDO pins on the module with a jumper.
  9. If you are on external power already, then you are hitting most probably the current limit of one of the power supplies. Since it sounds like you are increasing the frequency of the programmable logic, most probably the VCCINT supply (1.0V) is getting limited. Since power consumption is project-dependent, do a power analysis in Vivado with the implemented project. However, only very complex designs should be hitting the 2.6A current limit on the 1.0V rail. Your project might not even meet timing constraints anymore with high logic utilization and high operating frequency. In other words, you m
  10. You are most probably hitting the USB port power limit (you did not specify how you are powering the board). The Arty-Z7 RM applies to the PYNQ-Z1 as well: https://reference.digilentinc.com/programmable-logic/arty-z7/reference-manual#power_supplies.
  11. I added the maximum theoretical data rates for SATA (600MB/s) and PCIe (500MB/s) to the reference manual. I do not have benchmarks at the moment, but I recommend mSATA. Good mSATA modules should bench at least 200MB/s read speed.
  12. The Genesys ZU was validated with a 16GB 2Rx8 ECC module (SQR-SD4I16G2K4SEBB). The PS DDR4 controller is limited to 34GB, so theoretically a sixteen-component 2Rx8 module (32GB) would also work. Keep in mind that dual-rank components max out at a one step lower data rate (1600-3EG; 1866-5EV).
  13. The board in question will be replaced. Thanks for bringing it to our attention!
  14. While looking at this I found an issue in our Genesys 2 reference manual which was not detailing the PHY-internal delays in accordance with the schematic. I hope the revised section makes it clear now: https://reference.digilentinc.com/reference/programmable-logic/genesys-2/reference-manual#ethernet_phy. You have the RXDLY and TXDLY configuration straps wrong. Also double-check what delays does the MAC in your design introduce. The traces are matched to +-10ps. Package delays would need to be added, but considering a total +-50ps mismatch is conservative enough and will not be hard for th
  15. I believe those parameters are just for generating the example design, of which there is only one for that specific Xilinx TRD system.