elodg

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elodg last won the day on June 16

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About elodg

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  1. DDR2/DDR3 designs work fine without driver impedance control, even in non-point-to-point topologies. Maybe Xilinx considered that receiver termination is enough to cover all use cases and the board designer should provide that. In our point-to-point topology, we could achieve compliance with a much simpler driver impedance adaptation. We do not generally provide gerbers. If you think your use case is legitimate, contact us at https://store.digilentinc.com/further-assistance/ and we might be able to provide them under NDA.
  2. What you are saying is a tad too big of a leap. All I can say is that 22-ohm series resistor added to the driving impedance met the design requirements.
  3. Each design is validated independently. Any tactic can be employed as long as the DDR3 specifications are met. Ideally the line is terminated at both ends, and drive impedance matches line impedance and input impedance. Some designs only employ parallel receiver termination, others only series drive impedance matching. The Cora Z7 is the latter, the Xilinx dev kit is probably the former.
  4. From ug585 pg. 310: For DDR3 DCI calibrates the termination impedance and not the driver impedance. Series termination resistors is a form of drive impedance adaptation.
  5. Quoting from https://reference.digilentinc.com/reference/programmable-logic/anvyl/reference-manual#flash_memory: What makes you think it is only for FPGA configuration? Instantiate the AXI Quad SPI IP and map it to the pins called out in the RM and schematic.
  6. One can get lost pretty easily as the learning curve is steep and the same goes for us too. We are hard at work getting 2020.1 support published for G-ZU and we are seeing our fair share of issues. We do not have a BSP published, but the https://github.com/Digilent/Genesys-ZU-OOB-os repo should be just as good of a starting point. For now it is only for 2019.1 but we successfully created Ubuntu rootfs for internal use with it. It is our sole supported version at the moment.
  7. The best way would be a pull request on github, provided that the changes you did for FreeRTOS do not break standalone compatibility.
  8. elodg

    HDMI directly into FPGA

    Carefully evaluate your system requirements (resolution, link rate) and do board-level simulation on the TMDS signals. FPGA user I/O pins have considerable capacitance and might close your signal eye too much. Buffers like the TMDS141 help with decoupling cable segment from the PCB, making longer PCB traces possible. Our development boards are not HDMI-certified, but buffers might make passing electrical certification easier.
  9. @hendog82, give us some info on your setup. What Petalinux version are you using and what kernel and apps recipes you configured for ptp?
  10. Haven't seen low-level code in a while. Check the register reference in https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf. Page 1773 deals with these registers. The difference seems to be that SR is a read-only register reflecting real-time hardware status, while ISR is read and write-to-clear. ISR is used by the interrupt handler to handle the interrupt event and clear the status bits at the end then wait for it to be set again. If not cleared and the byte is consumed/produced, an erroneous interrupt will trigger again with no data to read/write. Xilinx's drivers are a good reference on how to use their peripherals programatically.
  11. Hi Blake, Our MIPI offering published at https://github.com/Digilent/vivado-library/tree/master/ip is a limited functionality implementation for those without access to the specs or licensed IP. We are commited to providing open-source implementations that people can learn from. The Digilent D-PHY Receiver works with the D-PHY I/O separated into LVDS high-speed and LVCMOS low-power buses, as implemented on the Zybo Z7. However, if you are looking for full-featured MIPI IPs, have a look at Xilinx's offering: D-PHY has been free for some time and CSI-2 just became free in Vivado 2020.1. Xilinx's D-PHY supports direct D-PHY I/O interfacing (UltraScale+) and LVDS/LVCMOS-separated (pre-UltraScale+). There are important restrictions on the system. Take a look here: https://reference.digilentinc.com/reference/add-ons/fmc-pcam-adapter/reference-manual#fpga_io_architecture_compatibility
  12. Microblaze has: AXI4 (M_AXI_DP) data side interface, AXI4 (M_AXI_IP) instruction side interface, AXI4 (M_AXI_DC) protocol for D-Cache, AXI4 (M_AXI_IC) protocol for I-Cache. The address editor should show EMC under the Instruction section if the EMC IP has a path to M_AXI_IP or M_AXI_IC. However, it is best to keep things simple: connect external memory to IC and DC, while keeping all the rest on DP.
  13. Right click the linker script, choose “Generate linker script” and you will have an easier option to link all sections to a different memory.
  14. Step “11. Verify Linker Script File for Memory Region Mapping“ of the guide calls for linking the whole application to the cellular ram, which is easier than trying to make it fit in the BRAM.
  15. Macro constants with XPAR_ prefix are automatically generated by the BSP for the hardware platform and written to xparameters.h. Open the header file and look for the interrupt definition. It should reflect the block design names and connections.