elodg

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elodg last won the day on August 27 2018

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About elodg

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  1. Assuming you instantiated with the default generics kGenerateSerialClk : boolean := true; kClkPrimitive : string := "PLL"; , you do not have to provide SerialClk to the module. The error message is complaining about CLKIN1 of the PLL generating SerialClk internally. CLKIN1 is actually PixelClk, so check where it is coming from and if it is a valid signal.
  2. Since you took the sources out the packaged IP and instantiated them as a module, please provide the generic parameters you instantiated with.
  3. From the IP documentation: Optional, if you enable the internal generation option in IP customization. If not, it must be generated external to the IP and provided on the pin.
  4. @Jonathan.O, I am seeing SPI signals in the code, not SD native. I though the whole point of this exercise is to have the interface with the lowest latency. In any case you have to get the init sequence right first. Either use ILA and Vivado Hardware Manager to debug the sequence, or switch back to Microblaze and software for easy debugging. Honestly I would do Microblaze just to have file system support. The init sequence is complicated with several modes and states the SD card can be in, wait times, status polls which are not easy got get right, especially in VHDL. Also confirm the clock speed is in the init range until the card is able to accept the maximum frequency.
  5. elodg

    Vivado sysnthesis fail..Pcam

    @Esti.A, 1. The timing error is localized to the DPHY input. The Digilent MIPI D-PHY IP is functional, but not optimized. Feel free to replace it with Xilinx's offering. 2. Just did a clean clone and re-did what the readme steps. Fixed the readme to ask for C++ instead of C, which I already told you in the issue you raised on Github. The workspace should look like this: 3. There is little we can do about SDK application crashes.
  6. Hello @Jonathan.O, SD cards usually only guarantee write bandwidth through class specifications. Usually we can extrapolate read performance too. However, all the performance levels are specified for SD native interface, not SPI. Since you mentioned library code, I suspect you are using the SPI-based IP from here: https://github.com/Digilent/vivado-library/tree/master/ip/Pmods/PmodSD_v1_0. Try an SD controller IP from OpenCores, see if it works better.
  7. elodg

    Vivado sysnthesis fail..Pcam

    The error is due to IPs and sub-IPs not being upgraded to the new version. I just posted a new release of the project which aligns the format with the digilent-vivado-scripts flow and upgrades everything to 2018.2. See here. Notice anything amiss? Post on issue on GitHub. It cannot be said often enough that Digilent only supports the Vivado version the project was released for. Furthermore, for a healthy dose of mental sanity, only one version is supported per year. For the year 2018 it is 2018.2, and not 2018.3 as @Ciprian said.
  8. I believe the behavior is due to the Zybo Z7 Petalinux BSP wrongly using 400kHz on the DDC bus to read out the EDID. Nexys Video does not provide an intelligible answer in this case. If you are in a hurry, try lowering the I2C0 speed to 100kHz. We will get around to fixing this eventually.
  9. Behavior confirmed. Will be looked at.
  10. Just to confirm, are we talking about Zybo or Zybo Z7?
  11. Hello @Suavek, I gave our SDSoC reVISION platform a try, because it is Linux-based and supports Pcam 5C. Booting the platform I get the following: root@Zybo-Z7-20:~# v4l2-ctl -d /dev/video0 --verbose --list-formats-ext VIDIOC_QUERYCAP: ok ioctl: VIDIOC_ENUM_FMT Index : 0 Type : Video Capture Multiplanar Pixel Format: 'YUYV' Name : YUYV 4:2:2 Index : 1 Type : Video Capture Multiplanar Pixel Format: 'UYVY' Name : UYVY 4:2:2 Index : 2 Type : Video Capture Multiplanar Pixel Format: 'NM16' Name : Y/CbCr 4:2:2 (N-C) Index : 3 Type : Video Capture Multiplanar Pixel Format: 'NV16' Name : Y/CbCr 4:2:2 Looking at the Petalinux BSP project that is used in our SDSoC reVISION platform too, v4l2 support for the Pcam5C is coming from Xilinx Petalinux recipes for the MIPI CSI2 Rx Subsystem and Video Processing Subsystem IPs: https://github.com/Digilent/Petalinux-Zybo-Z7-20/commit/59be69aa92699cc26083c2ece87c28e2991151b3 Unfortunately, both IPs require a license (either separate or included in the SDSoC license), if you are re-creating the hardware platform, but you can use it as reference. Build a new Petalinux project using our BSP and compare devicetrees.
  12. @MateoConLechuga, what I meant is that the OOB demo that the board is programmed with in factory correctly drives DisplayPort. Indeed, none of the source files we provide on Github work. Thanks for publishing your project.
  13. The out-of-box demo in the flash memory drives the DisplayPort out and you should see it working. The source files for the project are here, where Jon linked to. The issue with the DP IP in the demo was that it requires a license to generate a bitstream, so it was removed and re-published here. I am glad you made it work, I know the feeling of satisfaction when that happens. I am eager to find out what was actually wrong with what you were trying.
  14. Hello Blake, Sincere apologies for the process taking so long. I will have to ask for your patience again. @BogdanVanca will send you a test project for the Zedboard + FMC-HDMI combo and instructions on how to execute the tests that are also used in manufacturing. I have to commend you for the clear description of the problem and all the debug work you already did. The message quoted above is expected for the first run on a new FMC-HDMI. It is unrelated to your issue. Let's wait for the test project and see the results before we go further.
  15. elodg

    Nexys Video "Feet"

    https://www.fastenal.com/products/details/0146057 https://www.fastenal.com/products/details/28783