FlyMario

Members
  • Content Count

    8
  • Joined

  • Last visited

Everything posted by FlyMario

  1. Well, I added a clock and that made a ton of improvement. Now I do have the signals exactly as I wanted them. Thanks a lot guys! FlyMario
  2. Oh, wow I didn't include my timing diagram. What a newbie. So, the first 8 lines are from the C64's keyboard column lines. What happens is (from my theory) the the first 7 lines go low to see if any key is pressed. If it finds a value at all it sequences through all of the column lines accept for the 8th line (A7 Grey). As you can see, all of the lows are easy to pick out accept for last one. That line only goes high if a key is detected... However you can see that it goes low when it is its turn to send out a key. On the very bottom line (pink B7) is from the output of my Sparta
  3. Thank you so very much for your response! My word, I have so much to think about now. Exciting. I am really just having fun, playing with a fpga board and my Commodore 64. Way too old to start this as a new career. I am very thankful folks such as yourself are willing to spread you knowledge. So many new bookmarks to look at now Thanks Again, Pete
  4. There is no clock. I am using the signals from the kbd[7:0] to trigger the logic. Its strange if I am required to use one since it has worked perfectly until this new issue. I am all ears
  5. So, I am starting to get these errors during the Place & Route phase WARNING:Par:288 - The signal kbd<0>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<1>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<2>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<3>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<4>_IBUF has no load. PAR will not attempt to route this si
  6. FlyMario

    FPGA Clock

    Oh wow... thank you very much! This answers the whole point of my long winded question!
  7. FlyMario

    FPGA Clock

    Thanks a lot guys! I will get back to you. I guess I thought that when you have always block, and you are putting in a blocking statement such as A = B; that there must be some clock to check that B had a value to pass and unblock the statement. There are so many contradicting statements on how this works.Blocking statements seem they would cause things to run in Series instead of Parallel. Perhaps I am worrying about this too much. Also, anyone have experience with C64 logic levels think that if I put a 20k resister from ground to the fpga pin and then a 10k resister from the p
  8. FlyMario

    FPGA Clock

    I am learning how to program a FPGA (spartan) lately. The language I am using is Verilog which is not really important to this question. I have the FPGA connected to my Commodore 64 via Logic Level Converters. And I am having lot of success. I am reading 8 lines from the Keyboard port looking. My verilog is simply looking for a matching value on those lines. No problems at all. But I am curious, how is the logic managing to work when I have not really set up a clocking line. Is the FPGA using main clock to trigger events to move on in the FPGA. For instance, if you have a blo