• Content Count

  • Joined

  • Last visited

  • Days Won


Everything posted by jpeyron

  1. Hi @alien18331, Glad to hear you were able to get the hello world working! best regards, Jon
  2. Hi @bass2, Here is a xilinx forum thread and here that discusses the DAP status 30000021 error that should be helpful tracking down the issue. Are you using the Digilent board files? The Board files become the default setting when running block automation and correctly configures the zynq processor including the DDR. If not here is a tutorial for installing the board files. best regards, Jon
  3. Hi @Hari Krishna, Welcome to the Digilent Forums! We have a few ADC that would connect through the Pmod Port of the Atlys. The AD1 (2 channel 12 bit), AD2 (4 channel 12 bit) and AD5 (four channel 24 bit). The AD5 is the only one that meets the 16 bit metric. The Pmod AD5 communicates through SPI. Here are some projects done by Analog Discovery that might be helpful for your project. best regards, Jon
  4. Hi @dmeads_10, Welcome to the Digilent Forums! You will need to create a BOOT.BIN file. Here is an older but still relevant tutorial for the Zedboard(ZYNQ) that will work for the Arty-Z7-10(ZYNQ). It discusses how to take a HDL project an turn it into a BOOT.BIN. Does your HDL project work when configuring the Arty-Z7-10 through JTAG and the HW manager? best regards, Jon
  5. Hi @Johnnie White, Welcome to the Digilent Forums! Glad to hear you were able to figure out the issue. Thank you for sharing that disabling the XIP Mode was the fix for this situation. best regards, Jon
  6. Hi @skylape, I would suggest simulating your project. best regards, Jon
  7. Hi @youngpark, Welcome to the Digilent forum. Sorry to hear you are having issues with the Nexys Video. To verify the power-good LED (LD16) does not turn on when power(12 V) is given to the Nexys Video. Also the Nexys Video is not connected to anything else I.E. HDMI, FMC.... To better figure out where the issue is i would like you to measure the voltage of a few capacitors with a Digital Multi-Meter. either C329, C330, C331 or C332 ( should be 12.0 V) either C336, C337 or C338 (should be 3.3 V) either C344 or C340 (should be 1.0 V) either C348 or C349 (should be 1.8 V) either C354 or C355 (should be 1.5 V) best regards, Jon
  8. Hi @skylape, I believe the Verilog module should use the fastclk as a wire connecting the output from the clocking wizard to the pwm module. `timescale 1ns / 1ps module top( input CLK, output pwm_out1, output pwm_out2, output pwm_out3 ); wire fastClk; clk_wiz_0 clk_1 ( // Clock in ports .clk_in1(CLK), // Clock out ports .clk_out1(fastClk), // Status and control signals .locked() ); pwm pwm_output1 ( .clk(fastClk), .i_duty(10), .pwm_out(pwm_out1) ); pwm pwm_output2 ( .clk(fastClk), .i_duty(45), .pwm_out(pwm_out2) ); pwm pwm_output3 ( .clk(fastClk), .i_duty(80), .pwm_out(pwm_out3) ); endmodule You will also need an xdc file to constrain the input and output signals to pins on the FPGA. Here is the master xdc for the arty-a7. best regards, Jon
  9. Hi @alien18331, Welcome to the Digilent Forum! I would suggest to use/install the Digilent board file. The board files become the default setting when running block automation. After running block automation connect m_axi_gp0_aclk pin to the fclk_clk0 pin. I have attached screen shots of the process for getting the hello world project working. best regards, Jon
  10. Hi @sgandhi, Sorry i miss interpreted your earlier post. The main_gps_sd.c file attached below is for a zynq processor using the on-board SD card with out an interrupt and the Pmod GPS which should be helpful. best regards, Jon main_gps_sd.c
  11. Hi @KingJL, Welcome to the Digilent forum! We have contacted our content team and they are looking into this. Thank you for the input. best regards, Jon
  12. Hi @Devaraj, Welcome to the Digilent Forums! For the Pmod KPYD the rows are driven logic high and the columns are left floating and driven low when the corresponding button is pressed. As long as LVDS LVCMOS18 can overcome the pull ups there should not be an issue. You might want to drive the floating columns high using the pull-up iostandard in the ucf file. Here is the resource center for the Pmod KYPD. There are VHDL and Verilog examples for using the Pmod KPYD that should be helpful as well. best regards, Jon
  13. jpeyron

    GPS Pmod

    Hi @cepwin, Here is a verified Vivado 2019.1 Arty-S7-50 Pmod GPS on JB project that uses the Microblaze instead of the Microblaze MCS. best regards, Jon
  14. Hi @skylape, Welcome to the Digilent Forums! Here is how you would instantiate the clocking wizard with default names. In the below example there are 2 output clocks. clk_wiz_0 clk_1 ( // Clock in ports .clk_in1(CLK100MHZ), // Clock out ports .clk_out1(clk_out_100MHZ), .clk_out2(clk_out2_200MHZ), // Status and control signals .locked() ); end component; Here is a verilog project for the Nexys Video that used the clocking wizard. Here is a VHDL project that used the clocking wizard for the Arty-A7-35T. You can add the IP through ip catalog. best regards, Jon
  15. Hi @tauquir_iqbal, I moved this thread to a section where more experience Network Analyzer/Waveforms engineers look. best regards, Jon
  16. HI @Cherif, Welcome to the Digilent forums! Vivado projects are version specific. The Zybo-Z7-20-HDMI project is made for Vivado 2016.4. I have generated a bitstream and imported the application/bsp into SDK in vivado 2016.4. Here is the completed project. I can be found in the proj folder. I have attached screen shots and a picture with the project working. best regards, Jon
  17. jpeyron

    GPS Pmod

    Hi @cepwin, Is there a reason that you are using the Microblaze MCS instead of Microblaze? Here is a forum the discusses Microblaze and Microblaze MCS in regards to interfacing with the axi bus. best regards, Jon
  18. Hi @Niketan, Vivado's Webpack Edition is free and downloadable here baring some country restrictions. The Webpack works with the Arty-A7-100T. Here is the Arty-A7 resource center. Once you have downloaded vivado webpack edition , install the Digilent Board files as described here and you will be able to select the Arty A7-100T when creating a project. best regards Jon
  19. Hi @NotMyCupOfTea, I believe your options are either to build the filter or turning on the DSP filter on you oscilloscope(if you have that function available) as discussed in @hamster project. best regards, Jon
  20. jpeyron

    GPS Pmod

    Hi @cepwin, Welcome to the Digilent Forums! To better assist you I would like a little more information about your project. From the linker script I can see that you are using Vivado 2019.1 and Microblaze and not ZYNQ. 1. What FPGA development board are you using? a. If a Digilent FPGA are you using the Digilent board files? 2. Please attach a screen shot of your block design. Here is a verified Pmod GPS Microblaze project using Vivado 2019.1 and the Arty-A7-35T(Artix-7). I have also attached screens shots of the Block design, SDK, the block automation for microblaze and the tera term serial output. best regards, Jon
  21. Hi @Rom123, Glad to hear that installing the Digilent Plugin resolved the issue. Thank you for sharing what you did to fix this issue. best regards, Jon
  22. Hi @SuMatt, The Ethernet and the USB UART bridge is tied to the PS( ZYNQ Processor) and is correctly configured and constrained when running block automation with the Digilent board files. Here is a forum thread that discusses using the xemacps_example_intr_dma. I would also look into the driver resources here: C:\Xilinx\SDK\2019.1\data\embeddedsw\XilinxProcessorIPLib\drivers and here. best regards, Jon
  23. Hi @the_desperate_one, Welcome to the Digilent forums! I moved the thread to a section where the AD2/Waveforms engineers look. best regards, Jon
  24. Hi @NotMyCupOfTea, For higher frequencies i believe a reconstruction filter is needed as discussed in this thread here. best regards, Jon
  25. Hi @sgandhi, The ZYNQ processor is tied to the SD card reader. Are you using a Digilent ZYNQ development board? If you are using a Digilent Board you should be using the Digilent board files which will handle constraining the SD card. The zedboard programming guide tutorial covers how to make a BOOT.BIN and how to use it with the SD card reader. best regards, Jon