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Everything posted by jpeyron

  1. jpeyron

    hdmi ip clocking error

    Hi @askhunter, I did a little more searching and found a forum thread here where the customer is having a similar issue. A community member also posted a pass through zynq project that should be useful for your project. best regards, Jon
  2. Hi @Jzal, Glad to hear you were able to get the Pmod MTDS working. Thank you for sharing what you you did. best regards, Jon
  3. Hi @Zorroslade000, On step 4.8 of the Getting Started with the Vivado IP Integrator 1) In the Vivado block design add an additional uart lite ip core by clicking on the plus sign. 2) right click on the uart port on the uart lite and click on "make external" continue with the tutorial until step 5.2. 1) Add a constraint file by copying the Arty-A7-35T master XDC from ther XDC here. 2) Open the wrapper and find the signal names used for the uart rx and tx . 3) In the xdc alter the signal name of the pin/pmod port you would like to use. 4) un-comment the pins continue with the tutorial and generate a bitstream. Once you have launched SDK you will need to make your own code main.c. Look at the examples at the path here(for Vivado/SDK 2018.3 the path is below): C:\Xilinx\SDK\2018.3\data\embeddedsw\XilinxProcessorIPLib\drivers\uartlite_v3_2\examples best regards, Jon
  4. jpeyron

    hdmi ip clocking error

    Hi @askhunter, Please attach a screen shot of your vivado block design. Have you tried changing the MMCM to PLL in the DVI2RGB IP Core? best regards, Jon
  5. Hi @mjdbishop, Glad to hear the cable is working now! best regards, Jon
  6. Hi @Zorroslade000, Welcome to the Digilent Forums! Are you using the Pmod 232 on JA or a different IC? Please be more specific on what your project is trying to do. Here is the resource center for the Arty-A7-35T. The GPIO demo for the Arty-A7-35T here uses the usb uart bridge and communicates to the PC through a serial terminal. best regards, Jon
  7. Hi @askhunter, I believe that you would only need the more recent DVI2RGB IP Core and the IF folder in the Vivado library. best regards, Jon
  8. Hi @Bilal29, Here is a XADC VHDL project for the basys 3( can be altered to work with the nexys video) done by one of our community members @hamster that uses the XADC IP instead of the XADC wizard as you are looking to do. Sorry for the inconvenience. best regards, Jon
  9. jpeyron


    Hi @revathi, Unfortunately we have not work with the AMS_101. We would suggest to reach out to Xilinx about the AMS 101 mezzanine card. best regards, Jon
  10. Hi @ahmedengr.bilal, Try generating a bitstream without upgrading the IP Cores. best regards, Jon
  11. Hi @Mohammad12gsj, I have sent you a PM about this. best regards, Jon
  12. Hi @Kampi, Glad to hear you were able to get the video example working! best regards, Jon
  13. Hi @mjdbishop, I have PM'd you about this. best regards, Jon
  14. Hi @Bilal29, I do not have any experience using the XADC in ISE. Hopefully one of the more experienced community members will have some input for you in regards to ISE and the XADC. Is there a specific reason you are using ISE instead of Vivado? After re-reading your previous thread. If you were to use Vivado you can view the fpga temperature from the Hardware Manager in Vivado. Viewing the temperature is discussed and shown in this forum thread here. We also have a complete and verified XADC project or the Nexys Video on resource center here using Vivado. best regards, Jon
  15. Hi @Jzal, We should have some bandwidth to get the pmod MTDS working with the Arduino later today or early next week. While in the interim do you have an sd card installed into the Pmod MTDS with the appropriate files load? best regards, Jon
  16. Hi @Justen, Welcome to the Digilent Forums! I have passed on the change to our board files you suggest to our content team. Please attach a screen shot of your block design, wrapper and xdc file(if you are using a xdc file). Here is an older getting started with microblaze tutorial that might be helpful as well. best regards, Jon
  17. Hi @ahmedengr.bilal, We responded to your other thread here. best regards, Jon
  18. Hi @ahmedengr.bilal, Please attach screen shots of the errors you are getting. Did you follow the steps that chakma and bogdan state in the forum thread here? best regards, Jon
  19. jpeyron

    ZedBoard not turning ON

    Hi @Dimple, Sorry to hear that your boards is having issues. We can help trouble shoot where the issue is . Unfortunately we do not do repairs anymore. If we establish that going through the RMA process is appropriate we will need to know exactly when you purchased the Zedboard. Have you verified that the external power supply is working? Is there any part of the Zedboard the is pretty hot to the touch with it just powered on? Please measure the voltage of the following Capacitors with a DMM while the Zedboard is powered: either C328, C329 or C330 ( should be 5V) either C334 or C335 ( should be 3.3V) either C351 or C352 ( should be 1.5V) either C365 or C366 ( should be 1.8V) either C356 or C357 ( should be 1V) best regards, Jon
  20. Hi @zygot, Sorry for they late response. Thank you for taking the time to elaborate on the topic of select the right FPGA board. cheers, Jon
  21. Hi @conanandai100, We responded to your other post here. 1) Have you tried using the WIFI variant client/server projects? 2) Are you still experiencing the same issues? best regards, Jon
  22. Hi @Kalpitha, Welcome to the Digilent Forums! 1) What is your overall project goal? 2) Are you wanting to boot a project from the SD card? 3) Are you wanting to facilitate partial reconfiguration? 4) What development board are you using? best regards, Jon
  23. Hi @edge30, I have experienced similar issues when upgrading projects to newer versions of vivado. 1) I would suggest to start fresh with a copy of the original Vivado 2017.4 project. 2) Next I would open the project with the newer version of Vivado having Vivado upgrade the project. 3) Once the project is loaded in the newer version of Vivado, make sure that all of the IP's are upgraded by clicking reports->report ip status and upgrade/generate any IP that the report lets you. 4) generate a bitstream/ export hardware including bitstream (replacing the existing hw platform) and launch sdk. Does the project work as intended now? best regards, Jon
  24. Hi @nitish.moheeputh, Thank you for pointing this out. I fixed the above link to the zybo z7 resource center. The Zybo Z7 resource center is linked here as well. Let us know if you are still having issues with the links. best regards, Jon
  25. Hi @hearos, Glad to hear that you were able to get the linked project working. I also added the extern code to the Pmod OLEDrgb.h file. You should only need to incorporate the needed code from the main.c of the Pmod OLEDrgb to get that portion of the project working as well. best regards, Jon