jpeyron

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Everything posted by jpeyron

  1. jpeyron

    PmodSD

    Hi @BenBog, I am not aware of a way to speed up the write speed of the IP. I would suggest looking at the Xilinx SPI drivers here: C:\Xilinx\SDK\2019.1\data\embeddedsw\XilinxProcessorIPLib\drivers\spi_v4_4 and the AXI Quad SPI v3.2LogiCORE IP Product Guide. best regards, Jon
  2. Hi @huytergan, I would suggest looking at the Basys 3 GPIO demo The GPIO demo is done in VHDL and it uses the USB UART bridge. Here is the UART_TX_CTRL.vhd. best regards, Jon
  3. jpeyron

    Pmod SWT

    Hi @federicopy, Welcome to the Digilent Forums! I was able to get the Pmod SWT working with VIvado 2019.1 on JA with the Nexys 4. Looking at your block design it looks like you are altering the board files. I would suggest getting the project working before altering any of the board file settings. I have attach screen shots of most of the process in vivado, sdk and tera term output. Your main.c is altering the frequency? The GPIO_begin function in your main.c is setting the pins for output instead of input. You should be using 0xFF instead of 0x00. You can see this by looking at the GPIO_begin function in the PmodGPIO.c and how we call the GPIO_begin function in the two examples here. best regards, Jon Make sure to set the reset type to active low.
  4. Hi @NotMyCupOfTea, The usb uart bridge is tied to the PS in the Zybo-Z7-10. You will be using the zynq processor to send/receive data through the usb uart bridge. The Zybo-Z7-10-DMA, and Zybo-Z7-10-HDMI are bare-metal projects for the Zybo-Z7-10 that use the USB UART bridge. Initially, I would suggest starting with a more basic vivado project using the hello world template in sdk. Here are the basic steps to getting this project working in Vivado: 1. Makes sure the board files are installed and you select the zybo-z7-10 when creating the project. 2. create a block design 3. add the zynq processor and run the default(board files) block automation. 4. connect the axi-m-gp0-aclk pin to the fclk_clk0 pin on the zynq processor. 5. right click on the design in the sources tab and create a wrapper letting vivado handle it. 6. generate a bitstream. 7. Export the hardware including the bitstream. 8. Launch SDK in sdk: 1. once sdk has fully loaded with the hw_platform them click on file and add a new application. 2. give it a name and leave everything else as default. select next. 3. Select the hello world template. 4. program the FPGA 5. Open a serial terminal emulator like tera term and connect the com port of the Zybo-Z7-10. Make sure to adjust the baud rate to 115200 and typically leave all of the other settings at default. 6. right click on the application and select run as->launch on hardware(system debugger) and you should see hello world on the serial terminal!!!! best regards, Jon
  5. Hi @Zhanneta, Glad to hear that you have got the ethernet up and going! best regards, Jon
  6. Hi @marimo, Welcome to the Digilent forums! With the Nexys A7-100T you can either use the usb uart bridge or the ethernet to send the xadc data to the PC. I would suggest to either adapt the XADC demo to send data through the usb uart bridge or use the ethernet with microblaze. Here is a keyboard demo for the nexys A7-100T that uses the usb uart bridge. Here is an older tutorial that should help you get an echo server going. The other option would be the Pmod WIFI. best regards, Jon
  7. Hi @Zhanneta, Make sure that you are using the Cora Z7-07S Digilent board files. Here is a getting started with zynq servers that goes through the process for a Zybo(ZYNQ) that should work just fine for the Cora-Z7-07S. I just went through the tutorial on the Cora Z7-07S. I only thing I needed to do differently was comment out the lines //if ((eth_link_status == ETH_LINK_UP) && (!phy_link_status)) //eth_link_status = ETH_LINK_DOWN; If you do not comment out these lines the com port text just repeats that the ethernet link is up and then that the ethernet link is down. I believe this is related to the application looking for one of three specific PHY which is not used. These lines are in the ethernet_bsp(in the tutorial the application is called echo so it would be the echo_bsp): "ethernet_bsp\ps7_cortexa9_0\libsrc\lwip202_v1_1\src\contrib\ports\xilinx\netif\xadapter.c" Other than commenting out these lines, the echo server work just fine. I have attached screen shots of the Vivado 2018.2 block design, SDK and both tera term windows below. best regards, Jon
  8. jpeyron

    PmodSD

    Hi @BenBog, Welcome to the Digilent forums! To use the Quad mode you would want to start with a fresh Quad SPI IP Core set to Quad mode and constrain the pmod port pins through and XDC. Once you have generated a bitstream and have exported the hardware and launch SDK you should be able to use the libraries with some altering of the libraries to account for the change in the spi bus. Here is a forum thread that discussed using HDL to control the SD card that might be helpful as well. best regards, Jon
  9. Hi @Cherif, To clarify you were able to get the project running correctly in Vivado 2018.3? best regards, Jon
  10. Hi @bass2, Glad to hear that you were able to get your project working. Thank you for sharing what you had to do. best regards, Jon
  11. Hi @Antonio Fasano, We responded to your other thread here. best regards, Jon
  12. Hi @Antonio Fasano, Here is the xilinx recommended approach for sharing and archiving SDK that should be helpful for eliminating multiple hw platforms as well as having to use the same folder name. best regards, Jon
  13. Hi @stefantimm, We have added a CR1220 to the Pmod GPS. I will pass on your reference manual suggestion to our content team. Here is a forum thread that discusses the height of the battery as well. best regards, Jon
  14. Hi @Gary Perkins, Welcome to the Digilent Forums! Are you able to upload other sketches? Do you have the board and com port under tools selected correctly? best regards, Jon
  15. Hi @sgandhi, I believe the information is here as well. best regards, Jon
  16. Hi @skylape, I made a vivado 2019.1 Arty-A7-35T project using the pwm.v module and adjusting the top.v. I have attached a screen shot of the output on the first three pins on pmod Port JB. I have also attached the files I used and the generated bit file. best regards, Jon pwm.v top.v arty.xdc top.bit
  17. Hi @skylape, Please attach your Verilog top and pwm modules and i will see what i can do to get it working on an Arty-A7. best regards, Jon
  18. Hi @Miladsharif, Welcome to the Digilent Forums! Here is forum thread that deal with getting one of our pmods working with the Avnet's Microzed. I would also suggest reaching out to Avnet support. best regards, Jon
  19. Hi @skylape, Sorry for the confusion. I was referring to creating a testbench and simulating the project so to better see the signals. Here is a YouTube video about making a testbench. best regards, Jon
  20. Hi @ARD1996, Welcome to the Digilent Forums! We have not added a Pmod to the plug and play. Here is a tutorial for adding a new device. I would also look at the open and read functions in this search here. best regards, Jon
  21. Hi @bass2, Just to verify you have the Zybo-Z7-20 and not the Zybo or Zybo-Z7-10. Please attach a screen shot of your vivado block design as well as your SDK. best regards, Jon
  22. jpeyron

    SD Card EMIO

    Hi @Jocelyn Fauquet, Welcome to the Digilent Forum! I would try adding a delay into the FSBL in your project. The QSPI Flash might be trying to configure the FPGA before the power rails are stable. Here is a forum thread discussing this. It could also be something like an interrupt not being set up correctly like in this forum thread. best regards, Jon
  23. Hi @Frank Soucy, Welcome to the Digilent Forums! Another option is the Pmod JSTK2 IP Core available here that works with the Arty-A7 35T using Microblaze. best regards, Jon
  24. jpeyron

    ZYBO Image Processing

    Hi @birca123, Please be more specific about your parameters. We have the DVI2RGB and RGB2VGA IP cores that facilitate the hardware portion of the design. Are you looking for something using OpenCV and embedded linux. Here in an instructable that might be helpful. best regards, Jon
  25. Hi @Hari Krishna, Digilent does not have a 2 channel 16 bit ADC that is above 100 Msps. I would suggest using a 3rd party VHDC ADC to meet your needs. best regards, Jon