jpeyron

Members
  • Content Count

    5826
  • Joined

  • Last visited

  • Days Won

    244

Everything posted by jpeyron

  1. Hi @NotMyCupOfTea, I havent used a Custom IP in SDK. Here is a tutorial that describes using a Custom IP in SDK. best regards, Jon
  2. Hi @fasif, Please use the deb files here to install Adept 2 in ubuntu linux. The webpack edition works great with the Zybo development board as shown here. You do not need to use the Design Edition. best regards, Jon
  3. Hi @Tim S., Glad to hear that altering the case of the folders to all be the same resolves the missing files in the SDK and the project runs. Please clarify the issue with the Pmod KPYD. Does the multiple key pressed message show every time that you press a button? best regards, Jon
  4. Hi @hassan.ouayache, I haven't worked with the FIR Compiler. I would also suggest reaching out to Xilinx support. Hopefully one of the more experienced community members will have some input. best regards, Jon
  5. Hi @andre19, I have not worked with the SmartLynq Data Cable. With that being said I would suggest to make sure that ribbon cable is connected correctly on board and that you have the correct JTAG clock frequency. I would suggest reaching out to xilinx support. Hopefully one of the more experienced community members will have some input for you. Here is a xilinx forum thread that might be helpful. best regards, Jon
  6. jpeyron

    FAT32 with Zybo Z7

    Hi @sgandhi, Looking at you main.c did you tried using 1 instead of 0 in the f_mount function like this: f_mount(&fatfs, Path, 1); best regards, Jon
  7. jpeyron

    ZYBO Image Processing

    Hi @birca123, I am not aware of a stand alone library that would allow writing text on images and drawing objects. Here is a hackster.io HLS project and here is a HDMI VHDL project that could be helpful. best regards, Jon
  8. Hi @Yuval, Glad to hear that doing a re-boot of your computer fixed the issue. Thank you for sharing what happened. best regards, Jon
  9. Hi @NotMyCupOfTea, The Creating a Custom IP core using the IP Integrator tutorial will help you make a custom ip core. I would also suggest looking at the zynq book here as well. best regards, Jon
  10. jpeyron

    GPS Pmod

    Hi @cepwin, I'm glad you we able to get to the bottom of the issue. Thank you for sharing what happened. cheers, Jon
  11. Hi @Yuval, Have you done a full reboot of your computer? I had to do a full reboot of my computer to get the changes to take place. best regards, Jon
  12. Hi @PoojaN, Glad to hear that changing the usb cable fixed the issue! best regards, Jon
  13. Hi @Tim S., I created a Arty-A7-100T Vivado 2019.1 Pmod OLEDrgb and Pmod KYPD project. I have some screen shot's of the vivado block design, clocking wizard and SDK attached below. I did noticed your design_1_wrapper_hw_platform does not have the board folder. Are you using the digilent board files(install tutorial here)? best regards, Jon
  14. Hi @PoojaN, I believe that this error is stating that there is a sudden voltage drop as discussed in this xilinx forum thread. How are you powering the Cmod A7? If through the usb uart bridge have you tried using a different usb cable? best regards, Jon
  15. jpeyron

    pmod wifi

    Hi @harika, I do not see any reason you would not be able to use the switches to control what game is being played. You would need to alter the WIFI HTTPServer demo to facilitate this. best regards, Jon
  16. Hi @m3atwad, The VDD on the Pmod Ports is tied to the 3.3V power rail coming from the regulator. The 5V pin on the Arduino styled header comes directly from either the external or USB power based on the power jumper (JP3) setting and does not come from the power regulator. The schematic here on page 11 shows this. All of the I/O pins on the Arduino styled header go through the 3.3V regulator and are tied between bank 34 and bank 35 on page 8 of the schematic. best regards, Jon
  17. jpeyron

    FPGA

    Hi @gummadi Teja, Based on your previous posts you have a Nexys 4. We have an older basic tutorial on using the Microblaze processor. If it is a Nexys 4 DDR then here is a Nexys 4 DDR - Getting Started with Microblaze and if it is the Nexys 4 then it is the Nexys 4 - Getting Started with Microblaze. Here is the MicroBlaze Processor Reference Guide. The digilent board files (tutorial on installing here) correctly configure the microblaze processor best regards, Jon
  18. Hi @marimo, What version/edition of vivado are you using? What OS are you using? Are you running Vivado in a Virtual machine? best regards, Jon
  19. Hi @Mariam Rak, Welcome to the Digilent Forums. Here is the 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide. On page 22 it has information on configuration and use of the xadc. Here are XADC and XADC examples that should be useful. best regards, Jon
  20. Hi @jomoengineer, glad to here that you were able to get the PCAM 5C demo working on the Zybo-Z7-10. Thank you for sharing what you did to get this project working. best regards, Jon
  21. Hi @m3atwad, My understanding is that there is a 200 ma bank limit as discussed on page 4(note #10) of the Zynq-7000 All Programmable SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics. You can see that both pmod's I/O are connected to bank 34 as shown on page 8 of the schematic here. The VCC and Ground pins can deliver up to 100mA of current per pmod as discussed in the reference manual in section 12 Pmod Connectors here. best regards, Jon
  22. Hi @NotMyCupOfTea, Looking at the blinky project as well as what you describe with the uart project they are not using the Digilent Board files. This tutorial here shows how to install the Digilent Board files. The Zynq processor's default settings when selecting the Zybo-Z7-10 and running the block automation correctly configures the Zynq processor. It also has most of the components selected initially like the uart. You should be able to run the hello world without changing anything in the zynq processor. With the blinky project are you tying to add the verilog module to the zynq processor? If so you should be using the ADD a Module function like in your other thread here. best regards, Jon
  23. Hi @Azzor, Welcome to the Digilent forums. I downloaded the zip file for Vivado 2017.4 from the release page here. I opened Vivado 2017.4 cd'd to the correct folder and opened the project. I then generated a bitstream without issue. I have attached a screen shot of this. Are you using a different version of Vivado? Best regards, Jon
  24. jpeyron

    GPS Pmod

    Hi @cepwin, Where are you running the GPS project I.E. on a roof, in a park, in a building....? If in a building, how close to a window? If outside, could you be having issues with urban canyons? best regards, Jon
  25. Hi @fasif, Please install Adept 2 here. When running the terminal command djtgcfg enum what is the response. best regards, Jon