jpeyron

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Everything posted by jpeyron

  1. jpeyron

    AXI4 and Vivado ILA

    Hi @Sduru, Glad to hear that the problem has been resolved! best regards, Jon
  2. Hi @andre19, Welcome to the Digilent Forums. What ZYNQ development board do you have? I would suggest following the Getting Started with Zynq tutorial along with making sure that you have the Digilent board files installed. Digilent has board files that correctly configures the ZYNQ processor along with the DDR3. Here are the tutorials that we have available Getting Started with the Vivado IP Integrator, Getting Started with Vivado, Installing Vivado and Digilent Board Files and Getting Started with Digilent Pmod IPs. I will pass on your desire for more information on the Zynq core, AXI interconnect, GPIO, proc reset IP Cores to our content team although I believe that currently we do not have the bandwidth to create tutorials for how to edit properties of the Zynq core, AXI interconnect, GPIO and the process reset IP Cores. I would suggest looking through the Zynq-7000 SoC Technical Reference Manual, AXI Interconnect v2.1 LogiCORE IP Product Guide, Processor System Reset Module v5.0 LogiCORE IP Product Guide and AXI GPIO v2.0 LogiCORE IP Product Guide. Xilinx does have a lot of documentation/examples on how to use their IP Cores available from the block design by right clicking on the IP. I would also suggest looking here (if you used the default installation path): " C:\Xilinx\SDK\2018.3\data\embeddedsw\XilinxProcessorIPLib\drivers" for examples on how to uses their IP Cores in SDK. The ZYNQ book is also a good source of information as well. If you are still having issues with the Getting Started with Zynq tutorial please attach screen shots of your block design. best regards, Jon
  3. Hi @aliff saad, Please attach a screen shot of the Arduino IDE errors. Please attach the path of where you have install the LSM9DS1 library. best regards, Jon
  4. jpeyron

    DDR3 input clock source

    Hi @mishu, I believe we added the additional oscillator to help meet timing and eliminated propagation delays with the DDR3. I have reached out to a more experienced engineer to see if they have any additional input as well. best regards, Jon
  5. Hi @PallaviCharupallli, Here is is the resource center for the Zybo Z7. The DMA Audio Demo on the resource center should help with understanding how to use the audio codec. The Digilent board files correctly configure the Zynq processor along with the DDR which is tied directly to the ARM processors. I have attached an image to help visualize the ZYNQ processor architecture. Here is the ZYNQ book that should be helpful with better understanding the DDR and Audio codec. best regards, Jon
  6. Hi @Schuette, Please attach screen shot of your block design along with your project settings. Did you run block automation prior to trying to add the additional clock? best regards, Jon
  7. jpeyron

    xadc_zynq

    Hi @revathi, What is the Sample rate of the XADC. Please attach your SDK Code. best regards, Jon
  8. Hi @Tim S., It is good to hear that you you were able to over come this issue. Thank you for sharing what you found about the AXI4 and the AXI Stream. best regards, Jon
  9. Hi @HighEndCompute, I split your thread so that we can continue discussing this issue on a non closed thread. 1) Make sure the Jumper JP5 next to the power switch set to USB and the Mode Jumper JP4 is set to JTAG. 2) Next download Adept 2 here. Plug the USB A to micro B cable into the PYNQ-Z1 and a USB port on your PC. 3) Open Adept 2. Does adept 2 recognize the PYNQ-Z1 as shown in the screen shot below? 4) Have you tried using different USB A to Micro B cables and USB ports on the PC? best regards, Jon
  10. jpeyron

    JTAG-SMT3 Problems

    Hi @Carlos Posse, In your schematic you do not show the RTS or CTS signals. Do you have those signal attached? Also what do you have attached to the VBUS Detect? best regards, Jon
  11. Hi @Droplet DB, Unfortunately, we do not share the PCB layouts publicly. The XC7A200T-1SBG484C is the FPGA on the Nexys Video. The C means it is commercial grade for temperature . The commercial operational temperature range is 0 to 85 °C. best regards, Jon
  12. Hi @Tifei, I would guess you have seen this thread here. The adept software is not design to facilitate the usage of BSDL Files with the JTAG-HS2. I would suggest reaching out to Xilinx about Vivado. best regards, Jon
  13. jpeyron

    Zybo-z7-10 Step File

    Hi @hayesjaj, Unfortunately, we do not have a 3D model for the Zybo-Z7. We can provide you with caliper measurements if needed. best regards, Jon
  14. Hi @Kalpitha, Unfortunately, I have not worked with partial or full reconfiguration. Hopefully one of the more experienced community members will have some input for you. I would also suggest reaching out to Xilinx for more input as well. best regards, Jon
  15. jpeyron

    xadc_zynq

    Hi @revathi, Its my understanding that bipolar mode is -.5v to .5v instead of 0v to1v as described in the 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide on page 23. best regards, Jon
  16. jpeyron

    Nexys Video XADC

    Hi @Bilal29, VP and VN is connected to J18 and not JXADC as shown on page 9 of the schematic here. J18 is to the right of the on board OLED on the Nexys Video. best regards, Jon
  17. Hi @Justen, Our content team confirmed there was a typo in the board files causing an issue with the on board LEDs for the Genesys 2. I fixed the typo on our GitHub. There are 2 ways you can fix this issue. Either edit the xml file using a text editor. The board.xml file can be found here "vivado-boards\new\board_files\genesys2\H\board.xml" on line 424 from: TRI_O to TRI_T or re-download the board files from the Digilent GitHub here. thank you for letting us know about this issue. best regards, Jon
  18. Hi @Aamirnagra, Unfortunately, I have not worked with implementing the BLE protocol with HDL nor have i found any examples. We do have a Pmod BLE along with the Pmod BLE IP Core usable with microblaze that facilitates the uart communication. best regards, Jon
  19. Hi @Zorroslade000, Glad to hear that this worked for you. best regards, Jon
  20. jpeyron

    ZedBoard not turning ON

    Hi @Dimple, Unfortunately it sounds like the regulator is broken. I have PM'd you more about this issue. best regards, Jon
  21. Hi @Justen, I wanted to let you know that we altered the board files to reflect the LVDS clk signals and we are still researching the on board LED issue as well. best regards, Jon
  22. Hi @hearos, I do not have much experience with FreeRTOS projects. I would suggest reaching out to FreeRTOS about how to deal with both c and cpp files. best regards, Jon
  23. Hi @Tim S., We do not have more in depth guides or documentation that would better describe using the xilinx drivers. I would suggest looking C:\Xilinx\SDK\2018.3\data\embeddedsw\XilinxProcessorIPLib\drivers at to better understand how xilinx uses their IP cores. We would also suggest reaching out to Xilinx support about using their drivers as well. best regards, Jon
  24. jpeyron

    JTAG-SMT3 Problems

    Hi @Carlos Posse, Please attach a picture of your set up. Along with a screen shot of what the Vivado hardware manager see's. Please download Adept 2 here. Then use the command djtgcfg enum in a terminal and attach a screen shot of the responding text. best regards, Jon
  25. Hi @JBF12, Here is a forum thread where the customer is trying to access the LD_MIO LED from the FPGA that might be helpful for your project. best regards, Jon