jpeyron

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Everything posted by jpeyron

  1. jpeyron

    PCAM OV5640 Power

    Hi @Sduru, Are you sure that the Zybo-Z7 is on COM1? Typically COM1 is an internal com port. Also sometime the menu will not show initially. Did you try hitting the enter button? I typically use something like tera term or PuTTY. Have you tied using one of these serial terminal emulators instead of the SDK serial terminal emulator? best regards, Jon
  2. jpeyron

    Pmod wifi SDK problem

    Hi @rzsmi, The content team is aware that the Pmod WIFI has errors when using Vivado/SDK 2018.2 and Vivado/SDK 2018.3. They will address this issue when they have bandwidth. Unfortunately we do not have an ETA for when this will be done. The current suggestion/solution is to use Vivado 2017.4. We are sorry for any inconvenience this may cause. best regards, Jon
  3. Hi @qoolink, Welcome to the Digilent Forums! I was able to get a completed project without errors in SDK. I downloaded the release for Vivado 2018.2 here. Then opened the project in Vivado 2018.2 from \ZedBoard-FMC-Pcam-Adapter-2018.2-1\vivado_proj. Next generate a bitstream and export the hardware including the bitstream. After I launched SDK from Vivado 2018.2 1) add a new application call "FSBL" with default setting on the first page while selecting zynq_FSBL for the template on the second page of set up. 2) add a new application call "fmc_pcam_adapter_demo" with default setting except the language should be C++ the first page. On the second page of set up select empty template. 3) right click on the src folder of the fmc_pcam_adapter_demo and import the ZedBoard_FMC_Pcam_Adapter_DEMO with selecting Overwrite existing resources without warning. The read me attached below and in the project folder describes this process as well. I attached below a screen shot of the SDK project as well. best regards, Jon README.md
  4. Hi @Zhanneta, Glad to hear that you were able to get this project up and going in Vivado 2018.3. best regards, Jon
  5. Hi @FPGAMiner, Welcome to the Digilent Forums. We have not worked with Altera's IDE or on of their FPGA's. The GitHub link for the OdoCrypt FPGA Miner states under requirements that it currently only supports Intel (Altera) FPGAs on Linux hosts. We have not ported one of Altera's projects to work with Vivado/Xilinx FPGA's. We do have petalinux platforms for the Zybo Z7 here. I would think that after installing petalinux on the Zybo Z7 you would then need to duplicate their functions. Unfortunately we have no experience with this process and would not have useful advice. Hopefully one of the more experienced community members will have some helpful input for you. I would also suggest reaching out to the creator of the OdoCrypt FPGA Miner to see if they have any suggestions for getting this project working with a Xilinx FPGA. best regards, Jon
  6. jpeyron

    PCAM OV5640 Power

    Hi @Sduru, To clarify the situation, You are using a Zybo Z7-20 with the updated to Vivado 2018.2 PCAM-5C project. You are not able to get streaming video or the serial terminal menu. What OS and serial terminal are you using? Please provide screen shots of your block design, wrapper and SDK Code. best regards, Jon
  7. Hi @Zhanneta, This project was made in and for Vivado 2017.4. The easiest way to upgrade the Cora-Z7 project to Vivado 2018.3 is as follows: 1) Open the project in Vivado 2017.4. Make sure that your project has the vivado library installed in the repo folder. 2) Close the project and Vivado 2017.4 and open the project in Vivado 2018.3 having it upgrade the project for the newer version of Vivado. 3) Once the project has loaded. Upgrade the IP cores using the report->report ip status and generate the IP cores as well. 4) finally, generate a bitstream I have attached a screen shot of this project in Vivado 2018.3 with a bitstream generated. best regards, Jon
  8. Hi @Erickson, I believe these are the measurement you are looking for: Top edge of the Cora Z7 10 to the middle of J1 is 1.39 mm Top edge of the Cora Z7 10 to the top of J5 is 5.95 mm From the middle of pin 16 on J1 to the right edge of J5 is 2.54 mm 2x8 for J5 Best regards, Jon
  9. jpeyron

    PCAM OV5640 Power

    Hi @Sduru, It sounds like you were able to get the PCAM-5C working correctly as stated in your other thread here. Is that correct? best regards, Jon
  10. Hi @JLDIJDYI, Please link the manual you are referring to. I did not find anything referring to -5v to 5v or 0 to 10V adc in the Nexys A7 reference manual here. Here is the 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide. It is my understanding that you can either measure from 0-1v in unipolar mode or -.5v to .5v in bipolar mode. Please look at page 25-27 of the 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide for more detailed information. best regards, Jon
  11. Hi @andre19, 1) Its my understanding that you would not need to use the axi uart lite but rather the uart pins off of the ZYNQ processor. 2) Does your board have different mode settings. If so make sure that the mode is set to JTAG. best regards, Jon
  12. jpeyron

    JTAG-HS2 under linux

    Hi @Pavel_47, As long as Vivado and the cable drivers are installed correctly. I am not aware of any issues with using the JTAG HS2 with Vivado in linux. best regards, Jon
  13. Hi @postmaster87, This sounds like the power regulator is broken. I will send you a PM concerning this. best regards, Jon
  14. jpeyron

    xadc_zynq

    Hi @revathi, I am not quite sure why the Vp/Vn channel is not outputting as expected. I would suggest reaching out to Xilinx for more experienced input for the Xilinx's XADC , the XADC wizard and the ZC702. best regards, Jon
  15. jpeyron

    fpga kit

    Hi @NITISH KUMAR, The Atlys board is programmed by ISE iMPACT or Adept 2 as shown in the Atlys's reference manual here. The Atlys does not have an on-board user accessible ADC or DAC. We do offer ADC and DAC Pmods here that are compatible with the Atlys as well as our new Artix-7, Spartan-7 and Zynq development boards here. best regards, Jon
  16. Hi @Guacamoleroger, I found a link for Renaming hardware platforms causes compilation errors that look to be whats going on. We would suggest reaching out to Xilinx about this issue. I did find some other xilinx forum threads with similar issues here and here. best regards, Jon
  17. jpeyron

    pmod can period

    Hi @daeroro, Thank you for sharing a resolution to an issue with the Pmod CAN driver. We will pass this information on to our content team. best regards, Jon
  18. Hi @Thies, Welcome to the digilent forums! Thank you for sharing a resolution to an issue with the Pmod CAN driver. We will pass this information on to our content team. best regards, Jon
  19. Hi @Schuette, The reference manual for the Zybo Z7 here discusses this issue and explains that these critical warnings should be ignored. I get this critical warning every time i generate a bitstream with the zybo-z7. best regards, Jon
  20. Hi @Sduru, Glad to hear that you resolved the issue. Thank you for sharing what you did to resolve the issue. cheers, Jon
  21. Hi @jimge, Welcome to the Digilent Forums! Glad to hear that the Basys 3 is working. Thank you for sharing what you needed to do to resolve the issue. cheers, Jon
  22. Hi @gmodia, Welcome to the digilent forums! I moved your thread to a sub-section where more experienced embedded linux engineers look. best regards, Jon
  23. Hi @akash, Here is the Nexys 4 DDR Music Looper. This demo uses the clock wizard and HDL. best regards, Jon
  24. Hi @farideh, Welcome to the digilent forum. We responded to your other thread here. best regards, Jon
  25. Hi @farideh, We have not worked with GEM5 or dynamic voltage and frequency scaling. I would suggest reaching out to GEM5. I did find a paper that might be helpful here. best regards, Jon