jpeyron

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Everything posted by jpeyron

  1. For anyone looking through this thread the issue was resolved on this thread here. cheers, Jon
  2. Hi @k16blfurm, Glad to hear you were able to get your program to compile. Thank you for sharing it was a conflict between 32 and 64 bit libraries. best regards, Jon
  3. HI @Azzor, Glad to hear you are able to get the project working. Thank you for sharing that replacing the monitor resolved the issue. best regards, Jon
  4. Hi @mmdsaifudn, Welcome to the Digilent forums! I havent used the XIP more in the QSPI FLASH IP Core. Here is a tutorial for using the QSPI FLASH IP core. The tutorial explains how to compress the bit file as well as commenting out the verbose serial print to reduce the time it takes to configure the fpga from the QSPI Flash. Have you already compress the bit file and commented out the verbose? This improved the time it took to configure the fpga from the QSPI Flash significantly for my projects. best regards, Jon
  5. jpeyron

    Reprogramming Failure

    Hi @Alexela, Welcome to the Digilent Forums! I have sent you a PM about this. Best regards, Jon
  6. Hello, Based on @chainastole's other thread here the cable was power only and switching to a cable that had data resolved the issue. best regards, Jon
  7. Hi @osti, Welcome to the Digilent forums! I moved the thread to a section where more experienced Digital Discovery/WaveForms engineers look. best regards, Jon
  8. Hi @sabrina_n, I sent you a PM about this. cheers, Jon
  9. Hi @chainastole, Glad to hear that getting a USB A to MIcro B cable that does both power and data was the issue. Thank you for sharing what you did! best regards, Jon
  10. Hi @chainastole, Some of the USB A to Micro B only provide power and do not have the data lines connected internally in the cable. Some USB A to Micro B do have the data line connected. The easiest way to tell on a currently owned USB A to Micro B is to connect a device like a smart phone to your PC. If you are able to download files/pictures from the smartphone then the USB A to Micro B cable provides data as well. EDIT: Looking at your other post you did just this and the cable was the issue. best regards, Jon
  11. Hi @birca123, Sorry about that. here is the link. best regards, Jon
  12. jpeyron

    JTAG-SMT2

    Hi @Wyorin, Since you are able to initialize the scan chain and configure the Spartan 6 i would first look into the Chipscope ILA. I have not used the Chipscope ILA in ISE. This AR looks to be helpful for trouble shooting the Chipscope. best regards, Jon
  13. Hi @Mats, We have reached out to a co-worker about this thread. best regards, Jon
  14. Hi @core2explore, If the board is physically connected to the PC through the USB UART bridge or the JTAG port then remote desktop should not be an issue. I use my work PC remotely and configure connected FPGA's occasionally. best regards, Jon
  15. Hi @birca123, This article breaks down the uart controller on the zynq processor for a different zynq fpga. I believe this information should be applicable here as well. best regards, Jon
  16. Hi @andylb, Welcome to the Digilent forums! Unfortunately, no work has been done on LINX since late 2016 and there are not any plans to update the LINX driver for Raspberry Pi at this time. best regards, Jon
  17. Hi @core2explore, Is your project currently working through JTAG with sdk pulling the data from a file stored in flash? Here is a forum thread that discusses reading from the QSPI FLASH. Here is a tutorial for configuring the QSPI FLASH from SDK with microblaze projects. I would suggest compressing the bitstream. best regards, Jon
  18. Hi @Azzor, Have you tried using a different monitor? What selection are you choosing on the menu? best regards, Jon
  19. Hi @sungsik, Please elaborate on your overall project design and how you plan on using the aurora 64B66B. best regards, Jon
  20. Hi @kuppusamy, Welcome to the Digilent Forums! Here is a verilog XADC project done for the Basys 3. Here is a VHDL Pmod DA3 project for the basys 3 done by one of our community members. We unfortunately do not have any fir filter hdl. Best regards, Jon
  21. Hi @Jivoman, Welcome to the Digilent forums! I moved this thread to a section where more experienced AD2/WaveForms engineers look. best regards, Jon
  22. Hi @k16blfurm, Are you able to get an unaltered example working? best regards, Jon
  23. Hi @newkid_old, I'm not seeing anything directly wrong with your interrupts. Please attach a screen shot of you block design. Are you using the digilent board files? Are you altering any of the settings in the Microblaze processor? best regards, Jon
  24. Hi @k16blfurm, It looks like you are trying to read from the flash of a Cmod S6 using the dsumecfg function. I believe that Dsumecfg is used with the NETFPGA Sume as described in the the reference manual for the NETFPGA Sume. Here is a forum thread on how to program the flash on the Cmod S6 using iMPACT. Adept 2 only configures the Flash on a couple of the Digilent FPGA's. i do not believe that Adept 2 configures the FLASH on the Cmod S6 as shown in the screen shot of the Adept 2 GUI. Here is a xilinx thread that discusses programming FLASH from the command line using iMPACT. Here is a non-digilent tutorial on using Adept in the command line that might be helpful as well. best regards, Jon
  25. jpeyron

    XADC - AD7 sampled on AD14

    Hi @Kampi, Here is a forum thread that discusses using the PS with the xadc on the zedboard as well as the zybo. Are you able to run the hdl xadc project without issues? best regards, Jon