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Everything posted by jpeyron

  1. Hello D@n and Antonio, Sorry for the late response, we have been looking into this issue. We are thinking that the issue is the 4MB of quad spi flash. We are looking into compressing files to deal with this issue and should have something for you soon. thank you, Jon
  2. Hello, You should put your file in the last folder of the path C:\Program Files (x86)\Common Files\Digilent\AVRParts . thank you, Jon
  3. jpeyron


    Hi Isaac, Thank you for the clarification. I used tera term and pressed the button BTNL on the FPGA. thank you, Jon
  4. jpeyron


    Hi Isaac, The lscript.ld is a linker script that tells the program where to assign data, code and heap in memory. You can look here on how to create your own lscript.Id . I think you are asking for where the test pattern is in code. The test pattern is generated in the hdmi_demo.c with the function Pushbtnhandler. thank you, Jon
  5. Ailee, This is just my opinion, but the "in-between" microcontrollers have their place based on cost , ease of use and overall better functionality than the 8 bit but not as much as the ARM7. It depends on what you are trying to do and cost. thank you, Jon
  6. Hi paddy, Yes, if Synopsys has a command to change the jtag_tck then this will be able to change the HS2 or HS3 cables and you should not need to make you own api through Adept SDK. thank you, Jon
  7. Hello Southern Cross, I don't see a reason why they wouldn't. Most of the Pmods use either spi, i2c or uart which is see the beaglebone black supports. The beaglebone black doesn't have the pmod connectors so i would suggest using something like this to connect the Pmod to the appropriate pins. thank you, Jon
  8. FlyingBlindOnARocketCycle, We wanted the Basys 3, our introductory board, set at a low cost for the customer. Routing the MGT pins would have added cost to the board that we felt was not warrented. One option is our Nexys Video, which has the high speed MGT pins routed to a high speed connector, the FMC. thank you, Jon
  9. Miguel Rodrigues, There is some good documentation here , here for creating the axi IIC. Here is an example of the IP for the PmodAD2 here that uses IIC. Here you can download the PmodAD2 example project for the Nexys 3 in VHDL. It uses ISE 13.4 so you would need to do a little modifications to get it working in Vivado. I would use one of the Pmod headers JB- JF. If you use the reference manual for the PmodAD2 here you see the pinout description table to know how it is connected. Hopefully this helps! thank you, Jon
  10. FlyingBlindOnARocketCycle, That is correct. The MGT bank is not routed on the Basys 3. thank you, Jon
  11. Hello, I tested this design in vivado 2016.1 with not issue as shown below. Could you please take a screen shot of the error you found in the vga_r along with the errors you have with the design. The errors I am able to make out from you initial post seem to be related to trying to have led_4bits on both GPIO and GPIO2. thank you, Jon
  12. Hi Ben, The framework for the Adruino Due is writen and can be found in the link JColvin posted. You can uses the framework as a stepping stone to get the library working with the Arduino Zero. Unfortunately we never had an Arduino DUE to work with to confirm it working or not. Currently the AnlalogShield does not work on an Arduino DUE as shown here. thank you, Jon
  13. Hello Paddy, The jtag usb uses bit banging because of this there is no way to adjust the clock. We do have the jtag HS1 , jtag HS2 and jtag HS3 that have the ability to change the jtag_tck. You would need to contact Synopsis for the correct command to set the clock speed. Another route would be to make your own API using adept sdk that would allow you to set the clock speed for either of the jtag HS1 , jtag HS2 or jtag HS3. thank you, Jon
  14. Hello Harm, here is a link to a similar issue and how they seemed to fix issue. thank you, Jon
  15. Hello, I have emailed you the information you've requested for the trace lengths. You will have to account for the package skew and there will be some propagation speed differences based on the routing layers. These should be 50ohm+/-10%. Hoped this helps! thank you, Jon
  16. jpeyron

    Cmod S6 and LabVIEW

    Hello, Sorry for the late response, here is a link to the MakerHub Interface for Digilent Adept provides an easy-to-use API for communicating with Digilent FPGA Boards. Hopefully this helps! thank you, Jon
  17. Hello, Unfortunately, The AVR programmer support the following silicon: AT90USB162 AT90USB646 ATmega168 ATmega2560 ATmega48 ATmega64 ATmega165P ATmega88 ATtiny24 ATmega64 I’ve attached a document that describes how to create device files. It’s possible that a customer may be able to read the attached document and then write their own device file for the ATmega128 . Digilent AVR Part Description File Specification.pdf
  18. jpeyron

    SFP over vc709 Board

    Hi MOHIT, Looking at the 30-510 error, I think this post here should help you. Here is link to the user guide for the Virtex 7 vc709 board. We do not have a Virtex 7 vc709 board in house to be able to duplicate your error. We will still do whataver we can to help you but due to not having a Virtex board others in the community might be better able to assist you. thank you, Jon
  19. jpeyron

    HS3 HW_Server trouble

    Hello, Which version of Vivado are you using? Since you are not able to see the hardware target. It could be an issue with the cable, maybe cable drivers. Does the connect_hw_server command execute ok? thank you, Jon
  20. Hello, The overall size tolerances of the JTAG SMT2 are + or - .25mm on both the x and y plane. thank you, Jon
  21. hello, I confirmed this with our expert of the jtag-usb. Unfortunately the clock speed is set and can not be changed. thank you, Jon
  22. Hello, The is not recommended for the SUME. You need at least 75W and at the most 150W which this PCIe power supply does not give. I agree with JColvin that your best option then is to get a seperate PSU and follow the set up instructions at the link JColvin supplied. thank you, Jon
  23. Hello, Beyond the link that JColvin has for the "getting started with microblaze servers" here is some websites that have hdl examples of using the Ethernet port here and here. Unfortunately, there is currently nothing more than the Microchip based demo available for the PmodNIC100. thank you, Jon
  24. Hi Taisen, I was able to duplicate the error with your design. This is with microblazed local memory and cache set at 16k. If you up the local memory to 32k and keep the cache at 16k you will not get this error. thank you, Jon
  25. Hi Taisen, Sorry for the late response. Wanted to let you know we are looking into this situation and will be getting back to you as soon as we can. thank you, Jon