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jpeyron

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    Zedboard: USB-UART to PL

    in FPGA

    Posted

    Hi @moreabhinav,

    As described above in the diagram the PS is directly tied to  the USB UART.  Its my understanding that to use HDL(Verilog/VHDL) to send data through the USB UART  on a ZYNQ chip you would need to facilitate communication and the command protocols to and from the ARM processor. You would still be using the PS to send and receive date through the USB UART.  

    Can you be more specific about your project needs? 

    best regards,

    Jon

     

     

    CMOD a7-35t Schematic

    in FPGA

    Posted

    Hi @mzin92,

    I reached out to one of our design engineers about your thread and they responded :

    "For discrete parts without part number in the attached excel spreadsheet see the following requirements:

    All ceramic capacitors are temperature coefficient X5R, X7R or C0G, unless specified otherwise.
    Capacitors without maximum voltage rating are 6.3V or greater.
    Capacitors without tolerance specification are 10% (20% if 10% is unavailable) or better.
    Resistors without power rating are 1/16W or greater.
    Resistors without tolerance specification are 5% or better."

    best regards,

    Jon
     

    CMOD_A7_CAPS_AND_INDUCTORS.xlsx

    Zedboard: USB-UART to PL

    in FPGA

    Posted

    Hi @moreabhinav,

     

    Welcome to the Digilent Forums!

    To clarify, you are wanting to send and receive data between a PC and the Zedboard through the USB UART Bridge. The connector labeled UART ( J14 ). 

    The Zedboard has a ZYNQ processor. The USB UART bridge is connected directly to the ZYNQ Processor. Although it is not impossible to use the USB UART Bridge with VHDL/Verilog it is not a trivial task.

    I would suggest using the ZYNQ Processor to accomplish your task. The following steps will help you get a basic project using the USB UART bridge:

    1) Make sure you have installed the Digilent board files. 

    2) create a project and then a block design.

    3) Add the Zynq processor to the block design.

    4) Run block automation using the default settings which will be the board files

    5) Tie the FCLK_CLK0 pin to the M_AXI_GP0-ACLK pin

    6) right click on the block design in the sources tab and create a wrapper.

    7) generate a bit stream, export the hardware including the bit stream and launch SDK

    8). once in SDK create and application and select the hello world template. 

    9) Program the FPGA and right click on the application and run as -> launch on hardware(system debugger)

    Here is a slightly different tutorial that has the USB-UART bridge being used. 

    best regards,

    Jon 

     

    ZYNQ.jpg

    NEXYS A7 3D step file

    in FPGA

    Posted

    Hi @Yaacov,

    Welcome to the forums! Sorry for the delay in our response. We had to reach out to one of our layout engineers to convert the Nexys 4 DDR AD_ASM file we have into a STEP file.   We do not  currently have a STEP file for the Nexys A7 but we do have one for the Nexys 4 DDR. The Nexys 4 DDR is nearly identical with the Nexys A7. The STEP file for the Nexys 4 DDR (attached below) should work for making a case for the Nexys A7. 

    thank you,

    Jon

    Nexys_4_DDR.step

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