Forum Managers
  • Content Count

  • Joined

  • Last visited

  • Days Won


Everything posted by jpeyron

  1. jpeyron

    zybo image processing

    Hi @lokender, I believe this is stating that the bus width is different from the axi4 vid out and the stream_out-TDATA field. Here is a xilinx forum thread where they had a similar issue. Here is the Zybo resource center. Here is our SDSoC projects which has a sobel filter project for the Zybo but it is done in Vivado 2015.4. best regards, Jon
  2. Hi @Tim S., The IP Cores provided by Digilent should not have a cost. Here is a forum thread that describes these MIPI altered IP Cores. Are you able to generated a bitstream with the Zybo Z7-20 PCAM-5C project here(use the Vivado 2017.4 version)? I believe this project uses the same altered MIPI IP Cores. best regards, Jon
  3. HI @Grensv, Our design engineer looked at the attached logs and the endpCmd failed error message suggests a USB data transfer error. They suspect that this is related to using Virtual Box. Their only suggestion is to try running the dadutil or djtgcfg commands with sudo and see if it’s a permissions problem. best regards, Jon
  4. Hi @Ram, I believe it is the size of the tpcb which is used in the echo.c with the tcp_sndbuf and tcp_recv. I have attached an altered echo.c file that looks for two different strings and send a specific response when it gets the two different strings. best regards, Jon echo.txt
  5. Hi @jopho, I have not worked with a ZYNQ Ultrascale development board as of yet. Here is a forum thread on how to add a different FPGA family to an IP core. This thread should be helpful for adding the Ultrascale family to the DVI2RGB, RGB2DVI IP Cores. I am not aware of any architecture differences between the ZYNQ and the ZYNQ Ultrascale boards in regards to the DVI2RGB, RGB2DVI IP Cores here. best regards, Jon
  6. Hi @shahad, In Digilent Artix-7 fpga development boards like the Nexys 4 DDR you are able to use the USB UART bridge with VHDL/Verilog. Here is the resource center for the Nexys 4 DDR. Here is a Verilog project that uses the USB UART bridge with the Nexys 4 DDR. best regards, Jon
  7. Hi @Oblio, Welcome to the Digilent forums! Best regards, Jon
  8. Hi @Tim S., What version of Vivado are you using? The Zybo-Z7-20-base-linux project was created for and using Vivado 2017.4. best regards, Jon
  9. Hi @JamieJ, Welcome to the Digilent Forums! I moved your thread to a section where more AD2 experienced engineers look. best regards, Jon
  10. Hi @AndreaER, Welcome to the digilent forums! I have moved your thread to a section where more experience waveform engineers look. best regards, Jon
  11. Hi @Abdul Qayyum, I am not directly seeing anything wrong with your FSM. Here is a UART RX TX verilog module and here that should be useful for your project. best regards, Jon
  12. Hi @Grensv, To clarify you are using windows 7 with CentOS 6.10 running through Virtualbox 6.0.4 along with ISE14.7. I talked to one of our design engineers about this thread and they would like you to do the following: 1. In the terminal run the command "export ADEPT_RT_LOGDETAIL=1" 2. In the terminal run the command "export ADEPT_RT_LOGFILE=/home/YOUR_USERNAME_HERE/adept.log" 3. In the terminal re-run "djtgcfg enum". If it reports an error then a log file should be generated in the location that you specified in step 2. Please post the content of the error log here. best regards, Jon
  13. Hi @joniengr081, Here is a verified and completed LWiP Zybo-Z7-20 Vivado 2017.3.1 project. I followed the getting started with ZYNQ servers that is linked above as well as here. I have attached a few screen shots showing what I did. 1) Please open the linked Vivado project. 2) launch sdk. Once SDK is open program the Zybo-Z7-20. 3) Then alter your internet settings to facilitate the ethernet connection to your PC as described in the tutorial. 4) Then right click on the echo application and select run as-> launch on hardware(system debugger). 5) Next open tera term with TCP/IP selected then make sure that the host is set to then select Telnet and change the TCP port # to 7 and select ok. Does tera term show its connected? 6) Then click setting and terminal and change the tx to cr+LF and select local echo. 7) Now type stuff on the terminal and then press enter. Does it echo back the typed text? Best regards, Jon
  14. Hi @Grensv, Have you installed the digilent plugins here as well? Were you root while installing the Adept 2 rpm files? best regards, Jon
  15. jpeyron

    zybo image processing

    Hi @lokender, Welcome for the Digilent Forums! I am not seeing anything specifically wrong with your project. After generating the initial working project, i would suggest only altering one part of your desired changes so as to better trouble shoot the issues. I would also suggest using the the vivado library from here. Makes sure to be looking through the documentation provided in the vivado library for the IP Cores that are being used in this project. Here is a project that might be helpful as well. best regards, Jon
  16. Hi @Brayam Mamani, We have not work with GNU RADIO. I have found some information on the gnuradio wiki here and a project dealing with software defined radio on here that might be helpful. I found a paper here that should be helpful as well. Hopefully one of the more experienced community members will have some input on this topic. best regards, Jon
  17. Hi @Tim S., I was able to generate a bitstream using the zybo z7 base linux project from here. 1) I downloaded the project and then downloaded the vivado library and put the contents of the vivado library in the repo/vivado_library folder. 2) I then loaded the project in vivado 2017.4. 3) Then i upgraded/generated the IP cores using the report ip status under tools. 4) I then had to create a wrapper after which i was able to generate a bitstream without an issue. best regards, Jon
  18. Hi @YellowYoung, The last image you attach look like a working TX response through the USB UART bridge using something like tera term. Looking at main.c i believe it there is not a RX response then the project just sits waiting for a response. best regards, Jon
  19. Hi @joniengr081, Please attach screen shots of the UART and the telnet tera term terminals. Are you doing anything different from the tutorial such as loading the project from the SD card or QSPI using a BOOT.BIN file? best regards, Jon
  20. Hi @libswig, Looking further into this project there is no IP Core for the Pmod I2S2. The Pmod I2S2 is being used through Verilog. You should create a new project selecting the ZCU104. You should be able to use the Verilog without changing anything in Vivado 2018.3. You will need to use the attached XDC file as a reference for the ZCU104's XDC. best regards, Jon axis_volume_controller.v top.v axis_i2s2.v Cora-Z7-10-Master.xdc
  21. jpeyron

    Zybo hdmi

    Hi @adityasonavane7, Are you using the Zybo Z7 20, Zybo Z7 10 or the the original Zybo? We have HDMI projects for these boards linked on their resource centers here for the Zybo Z7 and here for the Zybo. We do have the DVI2RGB, RGB2VGA and RGB2DVI IP Cores available here which facilitates the HDMI protocol. We do not have tutorials on the HDMI protocol. The ZYNQ book here might be helpful. This tutorial here should be helpful as well. To better help you please be more specific and what your project is about. best regards, Jon
  22. Hi @Kerry Jones, 1) How are you powering the Nexys 4 DDR with an external power supply or usb cable ? Is the power select Jumper JP3 set correctly? 2) Have you tried using a different USB A to Micro B cable or external power supply? 3) Have you tried using a different USB port? 4)Are you using a USB Hub? 5) Have you tried a different PC or external power supply? 6) If the POWER LD 22 does not light up when the Nexys 4 DDR is on I would like to check the power rails coming out of the power regulator. 1) with a DMM please measure the voltage on the following capacitors: C178 (should be 5 V) Either C179 or C180 (should be 3.3 V) Either C183 or C184 (should be 1 V) C187 (should be 1.8 V) best regards, Jon
  23. Hi @YellowYoung, Welcome to the Digilent forums! The PmodCAN facilitates CAN communication to another device through the PL.The PmodCAN uses SPI communication to communicate between the host board and itself. It would not be able to connect to the CAN on the PS. To use the CAN bus on the PS you would need to use the MIO Pmod JE1 as discussed in the user guide for the Zedboard here in section 2.9.2 Digilent Pmod Compatible Headers (2x6). The user guide states the bank that the MIO pins are connected to a 3.3V bank so you would need to make a level shifting circuit for CAN communication to work since CAN uses voltage level as part of its communication. If all you need to do is communicate data from the Zedboard using CAN communication. Then you can send data from the PS to the PL and then send that data through the PmodCAN. Here is an Avnet forum thread that discusses sending data from the PS to the PL. Here is a Xilinx forum thread that initially discusses how they accomplished sending data from the PS to the PL. best regards, Jon
  24. Hi @vivekraj2992, Here is a forum thread that has a working project for the Genesys 2 using the QSPI Flash. best regards, Jon
  25. Hi @joniengr081, Please attach screen shots of your Vivado Block design, SDK. What serial terminal emulator are you using? Have you installed the digilent board files? The board files correctly configures the zynq processor. Are you selecting the Zybo-Z7-20 when you are creating the project? best regards, Jon