jpeyron
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Everything posted by jpeyron
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Hi @Bartowski, I have sent you a PM about this. best regards, Jon
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Hi @pank, I have sent you a PM about this. best regards, Jon
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Hi @Kolos Koblasz, Welcome to the Digilent forums! I have PM'd you about this issue. best regards, Jon
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Hi @AI Rabbit, Welcome to the Forums! I have pm'd you about this. best regards, Jon
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Hi @newkid_old, I updated and verified the project linked above for Vivado 2018.3. All you need to do is re-download the project from the link above. cheers, Jon
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Hi @moreabhinav, As described above in the diagram the PS is directly tied to the USB UART. Its my understanding that to use HDL(Verilog/VHDL) to send data through the USB UART on a ZYNQ chip you would need to facilitate communication and the command protocols to and from the ARM processor. You would still be using the PS to send and receive date through the USB UART. Can you be more specific about your project needs? best regards, Jon
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Hi @mzin92, I reached out to one of our design engineers about your thread and they responded : "For discrete parts without part number in the attached excel spreadsheet see the following requirements: All ceramic capacitors are temperature coefficient X5R, X7R or C0G, unless specified otherwise. Capacitors without maximum voltage rating are 6.3V or greater. Capacitors without tolerance specification are 10% (20% if 10% is unavailable) or better. Resistors without power rating are 1/16W or greater. Resistors without tolerance specification are 5% or better." best regards, Jon CMOD_A7_CAPS_AND_INDUCTORS.xlsx
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Hi @mzin92, There is no difference in the schematic on page 4 or 7 between the Cmod A7 15T anf the Cmod A7 35T. We do not publicly provide the BOM. What information are you looking for specifically? best regards, Jon
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Hi @mzin92, Welcome to the Digilent Forums! The schematic linked above is for both the Cmod A7 15T and the Cmod A7 35T. The regulator and rail information on page 7 of the Cmod A7 schematic is the same for either version of the Cmod A7 15 or Cmod A7 35T. best regards, Jon
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Hi @moreabhinav, Welcome to the Digilent Forums! To clarify, you are wanting to send and receive data between a PC and the Zedboard through the USB UART Bridge. The connector labeled UART ( J14 ). The Zedboard has a ZYNQ processor. The USB UART bridge is connected directly to the ZYNQ Processor. Although it is not impossible to use the USB UART Bridge with VHDL/Verilog it is not a trivial task. I would suggest using the ZYNQ Processor to accomplish your task. The following steps will help you get a basic project using the USB UART bridge: 1) Make sure you have installed the Digilent board files. 2) create a project and then a block design. 3) Add the Zynq processor to the block design. 4) Run block automation using the default settings which will be the board files 5) Tie the FCLK_CLK0 pin to the M_AXI_GP0-ACLK pin 6) right click on the block design in the sources tab and create a wrapper. 7) generate a bit stream, export the hardware including the bit stream and launch SDK 8). once in SDK create and application and select the hello world template. 9) Program the FPGA and right click on the application and run as -> launch on hardware(system debugger) Here is a slightly different tutorial that has the USB-UART bridge being used. best regards, Jon
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Hi @newkid_old, Here is a verified Vivado 2018.2 Arty-A7-35T gpio interrupt project using your SDK code. Please download and run this project. Do you get the expected results. If not please attach screen shots of your serial terminal output. thank you, Jon
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Hi @Korken, I sent you a PM about this. thank you, Jon
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Hi @lkamp, I have sent you a PM about this. thank you, Jon
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Hi @Christine Nason, I have sent you a PM about this. cheers, Jon
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Hi @ardent, I sent you a PM about this. thank you, Jon
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ADC/DAC higher than 2 MSPs and >= 12 bits (No FMC)?
jpeyron replied to herve's question in Add-on Boards
Hi @herve, I have passed on your 2 MSPs or higher ADC/DAC suggestion to the appropriate staff. thank you, Jon -
Hi @mishu, I sent you a PM about this. thank you, Jon
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Hi @hamidkavianathar, I sent you a PM about this. cheers, Jon
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Hi @yuki, I have sent you a PM about this. cheers, Jon
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ADC/DAC higher than 2 MSPs and >= 12 bits (No FMC)?
jpeyron replied to herve's question in Add-on Boards
Hi @herve, Digilent does not currently have either a DAC or an ADC that meets the 2 MSPS data rate requirement. If you are not able to use an FMC in the design then I would suggest to find a IC that meets the data rate needs with SPI communication and build a custom PCB to work with the FPGA development board you are using. thank,you, Jon -
Hi @tkb, I sent you a PM about this. cheers, Jon
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HI @Ahp, You will need to contact "support dot digilent at ni dot com" to further discuss acquiring the license for the programming solution. cheers, Jon
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Hi @wabo, Sorry about that. I have added you to the PM about this and removed @fapony. cheers, Jon
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Hi @Yaacov, Welcome to the forums! Sorry for the delay in our response. We had to reach out to one of our layout engineers to convert the Nexys 4 DDR AD_ASM file we have into a STEP file. We do not currently have a STEP file for the Nexys A7 but we do have one for the Nexys 4 DDR. The Nexys 4 DDR is nearly identical with the Nexys A7. The STEP file for the Nexys 4 DDR (attached below) should work for making a case for the Nexys A7. thank you, Jon Nexys_4_DDR.step
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Hi @Marty Squicciarini, Welcome to the forums. If you haven't seen the resource center for the AD2 here and the reference manual here. Here is the software for the AD2 Waveforms and its reference manual here. cheers, Jon
