jpeyron

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Posts posted by jpeyron


  1. Hi @Gabriel Uribe Romero,

    Welcome to the Digilent Forums!

    For discrete parts without part number see the following requirements:

    All ceramic capacitors are temperature coefficient X5R, X7R or C0G, unless specified otherwise.
    Capacitors without maximum voltage rating are 6.3V or greater.
    Capacitors without tolerance specification are 10% (20% if 10% is unavailable) or better.
    Resistors without power rating are 1/16W or greater.
    Resistors without tolerance specification are 5% or better.

    Let us know if you are looking for more specific information about a specific capacitor and we will see what we can do.

    If that is the case, please detail the individual capacitors that you are interested in I.E. C112 or C106...

    best regards,

    Jon


  2. Hi @Fabian,

    In the Datasheet here it states on page 16:

    "The temperature sensor block defaults to a power-down state.

    To perform a measurement, a measure temperature command is issued by the user to the control register (Register Address 0x80 and Register Address 0x81).

    After the temperature operation is complete (typically 800 μs later), the block automatically powers down until the next temperature command is issued.

    The user can poll the status register (Register Address 0x8F) to see if a valid temperature conversion has taken place, indicating that valid temperature data is available to read at Register Address 0x92 and Register Address 0x93 (see the Register Map section)."

    Please attach your code for reading the temperature.

    best regards,

    Jon


  3. Hi @user2051,

    Please download Adept 2 here.

    Does Adept recognize the Zybo-Z7? 

    I do not think I have seen this error before.

    Please attach a screen shot of your SDK with the hardware platform expanded.

    First right click on the BSP and select re-generate the board support package. If this does not work I would delete the SDK folder from your project and re-export the hardware from Vivado including the bitstream and start fresh.  

    If you are still experience this issue I would suggest reaching out to Xilinx support here

    best regards,

    Jon

     


  4. Hi @kavya@iiitn,

    Please attach a screen shot of your block design as well as the contents of the SD card you are using with the HTTPServer example.

    What FPGA board are you using?

    best regards,

    Jon


  5. Hi @Alex_V,

    In the attached picture the Mode Jumper is set to QSPI Flash.  JTAG Mode is the middle 2 pins.  I would suggest using the JTAG Mode to ensure there is no issues when configuring the FPGA.

    Here is a screen shot of my windows device manager with a Digilent FPGA connected. I previously miss spelled the word ports as pots. You should see a com port for the FPGA as well as serial converter A and B when your Nexys A7 is connected to your PC and powered on as shown below.

    image.thumb.png.d67545745f151c553e54143a1d2cead3.png

     

     

    On 6/24/2019 at 12:17 AM, Alex_V said:

    Each time I am trying to download the Bit Stream all steps in Vivado are performed correctly but the board does not act as expected. Does not act as it acted before.

    What about the project is not working or acting differently? 

    What type of project are you doing?

    Have you tried powering the board through an external power source? 

    Have you tried using your Nexys A7 on your friends PC?

    best regards,

    Jon

     


  6. Hi @pgmaser,

    Welcome to the Digilent Forums!

    You can use the ADD a Module function to connect a HDL module/entity to the axi bus using microblaze . Here is a forum thread that discusses this option.

    All of our boards use USB 2.0. The Nexys Video which has the Artix 7 fpga can be used with Gigabit Ethernet.  Here is a community members gigabit project with the Nexys Video.

    Best regards,

    Jon


  7. Hi @Ahmed Alfadhel,

    We have not had the bandwidth to create an IP Core for the Pmod CLP. We have verilog and VHDL ISE projects that can be alter to work with vivado on the Pmod CLS resource center . You will need to use the UCF file as a reference for the XDC file.

    You should be able to use the ADD a Module function in the Vivado Block design as discusses in this forum as well as in this xilinx YouTube to use these projects with Microblaze. 

    You can use the add a module function as described in this Xilinx YouTube. The add a module function allow users access to the AXI bus with their VHDL Entities/Verilog Modules.  Here is a forum thread that discusses this as well.

    best regards,

    Jon


  8. Hi @hiroowada,

    The master XDC for the Nexys A7 100T is here. The system clock pin is titled CLK100MHZ as show below:

    ## Clock signal

    #set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]

    #create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }];

    I would suggest not altering the boards files since they are already configured to work correctly with the Nexys A7.

    best regards,

    Jon

     

     

     


  9. Hi @Alex_V,

    Welcome to the Digilent forums!

    Please elaborate on what is not working or the odd behavior.

    Have you tried using different usb cables?

    Is the mode jumper set to JTAG? 

    What does the Nexys A7 show up as in the device manager under pots and universal serial bus controllers?

    best regards,

    Jon


  10. Hi @Y_H,

    Are you tying to add the Pmod DA3 to the Jupyter Notebook platform from PYNQ.io ?

    Are you trying to use the PYNQ with the ZYNQ processor in Vivado?

    Here is the resource center for the Pmod DA3.

    If you are trying to use the PYNQ board with vivado unfortunately we haven't had the bandwidth to create an IP Core for the Pmod DA3.

    Here is a VHDL project  done by a community @hamster that can be used with the ADD a Module function and the ZYNQ processor in the bock design in Vivado.

    Here is a Xilinx YouTube video that should help with using the ADD a Module function. 

    best regards,

    Jon