jpeyron

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Posts posted by jpeyron


  1. Hi @M.Mahdi.T,

    Welcome to the Digilent Forums!

    We typically do not test the max throughput metric when validating our products.

    Looking at the AD5933 datasheet here  the Pmod IA would be limited to 1 MSPS due to the on board ADC.

    The main bottleneck for throughput to a host board will be the I2C communication which runs at 400 KHz.

    Here is a good forum thread for using the Pmod IA with the Raspberry PI with code and hints for use , setup and calibration. Here is the resource center for the Pmod IA which has the Raspberry PI code as well.

    best regards,

    Jon

     


  2. Hi @PG_R,

    I have connected many different fpga's to my PC through Ethernet using a standard Ethernet cable.  I believe a regular ethernet cable will do just fine. The difficult process will be facilitating the ethernet communication. That is why I suggested using the petalinux project linked above.

    best regards,

    Jon  


  3. Hi @Allan Flippin,

    If you use the Arty-A7 35T or 100T or the Arty-S7 50T or 25T you can use a HDL(Verilog/VHDL) UART controller to communicate through the USB UART bridge. 

    ZYNQ FPGA's have some of the components on the board tied directly to the Arm processor(PS). The DDR3 and USB UART bridge would be included in these components. With ZYNQ FPGA's you can not use the PL to directly use the USB UART bridge. I have attach an image that is a good reference on the ZYNQ processor.  

    To use the USB UART bridge with the Arty-Z7 20 or Arty-Z7 10 you would need to use the Zynq processor. 

    Here is the getting started with ZYNQ tutorial for the Zybo that can easily be used with the Arty-Z7 . The GSWZ tutorial shows how to use the PS to communicate through the USB UART bridge.

    Here is the Arty-Z7 , Arty-A7 and Arty-S7 resource centers.

    best regards,

    Jon

    ZYNQ.jpg


  4. Hi @vttay03,

    I have not been able to be able to get the Hello world template to work with the QSPI flash with either the Arty-A7 35T or the Arty-A7-100T in Vivado 2018.3. I will keep looking into this issue with Vivado 2018.3. For now I would suggest using Vivado 2017.4. I was able to complete and verify the Hello world template project into the QSPI flash on the Arty-A7-100 using Vivado 2017.4.  I attached some screen shots of the programming setting in SDK. Also the offset is 0x003D0900 since the HW platform size is the same as the Nexys 4 DDR which has the same FPGA.

    best regards,

    Jon 

    Arty-A7-100-QSPI-2.jpg

    Arty-A7-100-QSPI-1.jpg


  5. Hi @hmd,

    I opened my VM and looked opt/ from the root directory. It has the Xilinx/ directory. I think it would be best to uninstall and re-install Vivado an leave it to default settings. Make sure that you are root while installing Vivado to insure there is no issues with permissions.

    best regards,

    Jon

    Vivado_linux_path.jpg


  6. Hi @Allan Flippin,

    It's my understanding that there is no current plans on adding access to the memory like for the newer families of FPGA's in Adept 2.  I am also not aware of any other application that facilitates that type of interaction with memory.  

    If using the USB UART bridge is a feasible alternative, could you be more specific about your data rate needs for transferring/receiving data to the PC? 

    There are quite a few HDL(VHDL/Verilog)  UART Controllers available with a quick google search. We also have projects that transfer data through the USB UART bridge using HDL like the Arty-A7 100T GPIO demo.  

    This older tutorial uses the Microblaze processor and uart lite IP Core that uses the USB UART bridge as well.

    best regards,

    Jon


  7. Hi @ToronoCoyo,

    Welcome to the Digilent Forums!

    Typically for more complicated projects such as the PCAM project doing connection automation with the same IP Cores alone will not create a HW platform that will correctly interact with the desired components. 

    Can you include screen shots of your block design and SDK applications and any errors along with wrapper, xdc  and SDK helloworld.c files.

    What is the Mode Jumper(JP5) on the Zybo-Z7 set to?

    If you are trying to boot from the SD card on a ZYNQ development board like the Zybo Z7 you should be making a boot.bin file.

    Booting from either SD card or FLASH process is described in this older zedboard tutorial

    best regards,

    Jon


  8. Hi @Allan Flippin,

    Adept 2 and Adept 2 SDK does work with Artix-7 based FPGA boards. Some of the functionality that was available for older FPGA's in Adept's UI was not done for the newer FPGA.  The Vivado Hardware manager can write to FLASH and can read ILA files. 

    The ILA IP Core  which is Vivado's version of chipscope is available at no cost with the free Vivado Webpack edition. Here is a good reference to what is available for each Vivado edition

    You can also use the USB UART bridge or ethernet to transmit/receive data from a PC using Microblaze or HDL for non-zynq families and the Zynq Processor with Zynq FPGA's. 

    I have used the USB UART bridge and serial terminal emulator(tera term) to send/receive data for trouble shooting issues in Artix-7 project development.  

    best regards,

    Jon

     


  9. Hi @jaypdx,

    You should either turn off the HDMI monitors that are connected to the Arty-z7 or unplug the HDMI cables prior to turning off the Arty-Z7. You can back power the Arty-Z7 through the HDMI connectors. This can cause potential issues with the Arty-Z7 startup power sequence which could affect your project. Its my understanding that back powering could potentially cause damage as well. 

    best regards,

    Jon


  10. Hi @jaypdx,

    Welcome to the Digilent Forums!

    Vivado projects are version specific and are not always easily upgraded to a different Version of Vivado. In this case, both the HDMI-OUT for the Arty-Z7-20 and the Arty-Z7-10 were last updated to "Vivado 2018.2".  It does sound like you have upgraded it correctly since you are able to get it to work.

    I would suggest to press PS-RST button which is connected to a dedicated pin on the FPGA. The PS-RST button will reset the Processing system of the Zynq. I believe you should be able to re-run the application without an issue after you press the PS-RST. 

    best regards,

    Jon


  11. Hi @Anusha Kodimela,

    You can design a converter in your hdl which takes in binary 8 bit value from the FIFO and converts it to ascii hex before transmitting to the PC using the USB UART bridge. The other option is once you have transmitted the data to the pc you can use a program to convert the 8 bit data to ascii hex and then read it on the terminal.

    best regards,

    Jon  


  12. Hi @SeanS,

    Did you install the Digilent board files as discussed above? In project creation make sure to select the boards you are using. The digilent board files become the default settings when you do block automation with added IP Cores like microblaze and the MIG. I have added a screen shot of the MIG setting that was automatically generated because of the board files.

    best regards,

    Jon

    Arty_A7_100_MIG_11.jpg

    Arty_A7_100_MIG_10.jpg

    Arty_A7_100_MIG_9.jpg

    Arty_A7_100_MIG_8.jpg

    Arty_A7_100_MIG_7.jpg

    Arty_A7_100_MIG_6.jpg

    Arty_A7_100_MIG_5.jpg

    Arty_A7_100_MIG_4.jpg

    Arty_A7_100_MIG_3.jpg

    Arty_A7_100_MIG_2.jpg

    Arty_A7_100_MIG_1.jpg


  13. Hi @TerryS,

    Thank you for posting how you got to the legacy content. I will pass this on to our content team. We will still have this content accessible since there are a wide array of people that use different versions of vivado. The legacy content is accurate for earlier versions of Vivado/SDK.

    best regards,

    Jon


  14. Hi @Anusha Kodimela,

    I talked with one a more experienced co-worker about your thread.

    Looking at the HDL and the attached simulations they think that the data coming out of the FIFO needs to be encoded into asci hex before transmitting the data to the PC or use some kind of program on the PC side to convert the data to asci hex before reading the data in a serial terminal emulator. 

    best regards,

    Jon