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Everything posted by jpeyron

  1. Hi @newkid_old, I would suggest using the ILA module. Here is a Xilinx forum that discusses this. Here is the Integrated Logic Analyzer v6.2 LogiCORE IP Product Guide that should also be helpful. Best regards, Jon
  2. Hi @thk3695, I sent you a PM about this. best regards, Jon
  3. Hi @brian.dig, Glad to hear that you were able to to download the SOV. best regards, Jon
  4. Hi @AndyCap, Glad to hear you were able to get past this issue. Thank you for sharing what you did. best regards, Jon
  5. Hi @brian.dig, Welcome to the digilent forums.! I have PM'd you a copy of the SOV for the JTAG-HS3. Please let us know if you were able to download this. Best regards, Jon
  6. Hi @Y_H, The Jupyter Notebook platform along with adding additional Pmod's to this platform is supported by PINQ.IO . You will need to reach out to PYNQ.IO Support here. best regards, Jon
  7. Hi @mptcultist, Are you able to run the Getting started with Microblaze tutorial working? best regards, Jon
  8. Hi @mptcultist, What text is being sent through the USB UART COM Port and the telnet on the Serial terminal emulator? Please attach screen shots. What speed are you setting the phy_link_speed? best regards, Jon
  9. jpeyron


    Hi @Ahmed Alfadhel, We have not had the bandwidth to create an IP Core for the Pmod CLP. We have verilog and VHDL ISE projects that can be alter to work with vivado on the Pmod CLS resource center . You will need to use the UCF file as a reference for the XDC file. You should be able to use the ADD a Module function in the Vivado Block design as discusses in this forum as well as in this xilinx YouTube to use these projects with Microblaze. You can use the add a module function as described in this Xilinx YouTube. The add a module function allow users access to the AXI bus with their VHDL Entities/Verilog Modules. Here is a forum thread that discusses this as well. best regards, Jon
  10. Hi @hiroowada, The master XDC for the Nexys A7 100T is here. The system clock pin is titled CLK100MHZ as show below: ## Clock signal #set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100] #create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }]; I would suggest not altering the boards files since they are already configured to work correctly with the Nexys A7. best regards, Jon
  11. jpeyron


    Hi @Alex_V, Welcome to the Digilent forums! Please elaborate on what is not working or the odd behavior. Have you tried using different usb cables? Is the mode jumper set to JTAG? What does the Nexys A7 show up as in the device manager under pots and universal serial bus controllers? best regards, Jon
  12. Hi @andre19, We have not worked with the ETTUS 310. We would suggest reaching out to ettus's support since they would have more experience with this board. best regards, Jon
  13. Hi @user2051, I am using Windows 7. I found AR# 69076 that discusses this here. I did also ind a xilinx forum that might help with this issue and have a solution here. best regards, Jon
  14. Hi @LSR, I would think that most current microcontrollers in the market will be able to meet all your needs except size. All of our microcontrollers here should meet all of your needs except size. These microcontrollers should fit your size needs as well: UC32, MAX32, Cmod MX1, WI-Fire or the WF32. best regards, Jon
  15. Hi @itlki, Welcome to the Digilent Forums! We have reached out to an engineer more experienced with the DMM Shield. While we are waiting for their input Here is the DMM Shield's resource center. Which library are you referring to? Arduino DMM Shield Library User Guide PIC32 DMM Shield Library User Guide Zynq DMM Shield Library User Guide Can you be more specific where in the library your concern is? best regards, Jon
  16. Hi @Y_H, Are you tying to add the Pmod DA3 to the Jupyter Notebook platform from ? Are you trying to use the PYNQ with the ZYNQ processor in Vivado? Here is the resource center for the Pmod DA3. If you are trying to use the PYNQ board with vivado unfortunately we haven't had the bandwidth to create an IP Core for the Pmod DA3. Here is a VHDL project done by a community @hamster that can be used with the ADD a Module function and the ZYNQ processor in the bock design in Vivado. Here is a Xilinx YouTube video that should help with using the ADD a Module function. best regards, Jon
  17. jpeyron

    Pmod wifi

    Hi @kavya@iiitn, What type of security is your router/modem using? best regards, Jon
  18. Hi @user2051, I can confirm that the UART block is not correctly configuring the zynq processor of the Zybo-Z7-20 in vivado 2015.2. from the boards files. I have reached out to our content team about this. I can confirm that newer versions of vivado 2017.4 and up correctly configures the zynq processor on the Zybo-Z7-20. I tried with no success to manually select uart1 in the zynq process in vivado 2015.2 and configure uart1 as shown in the vivado 2018.2 zynq processor attached screen shot. best regards, Jon
  19. Hi @lwew96, We have not used a reconstruction filter. I did find a paper that discusses a reconstruction filter with the AD5541 here. Hopefully one of the more experienced community members will have some input for you as well. best regards, Jon
  20. Hi @cfsterpka, You are correct the drdy_out signal tell us when data is ready to be read from the XADC. In the XADCdemo.v for the Arty-Z7-20 xadc project the wire ready is the output signal from the xadc wizard: wire ready; //XADC port that declares when data is ready to be taken xadc_wiz_0 XLXI_7 ( .daddr_in (Address_in), .dclk_in (clk), .den_in (enable & |sw), .di_in (), .dwe_in (), .busy_out (), .vauxp12 (xa_p[0]), .vauxn12 (xa_n[0]), .vauxp0 (xa_p[1]), .vauxn0 (xa_n[1]), .do_out (data), .eoc_out (enable), .channel_out (channel_out), .drdy_out (ready) ); best regards, Jon
  21. Hi @kotra sharmila, Were you able to get the SDSoC OpenCV project working from your other thread here? best regards, Jon
  22. jpeyron

    pmod wifi

    Hi @harika, I downloaded Vivado 2016.1 and completed/verified this Zedboard/WIFI/SD Vivado 2016.1 project. To get this project working: 1) Open this project in Vivado 2016.1. 2) launch SDK 3) Alter these specific lines in the HTTPServerConfig.h to reflect your modem login/password: const char * szSsid = "Your modem login"; const char * szPassPhrase = "Your modem password"; 4) After altering the HTTPServerConfig.h then save file. 5) Open and set up your serial terminal. 6) Program the FPGA and right click on the HTTP application and select run as->launch on hardware(system debugger). 7) To access the HTTPServer you will need to have a device that is connected to the same WIFI network. 8). Use the information given in the serial terminal to access the address of the HTTPServer. Let us know if this is not working for you. Make sure that the Mode jumper are set to JTAG and that the Pmod WIFI is on JC. The mode jumper needs to be set to JTAG since that is how the FPGA is being configured. Setting the mode jumper to SD would have the Zedboard looking for a BOOT.BIN file in the SD Card that would configure the FPGA from. There is no BOOT.BIN file created for this project. The WIFI project uses the SD card but does not configure the FPGA from the SD Card. Here is the Zedboard resource guide that goes into more detail for the mode Jumper settings on page 27 . best regards, Jon
  23. Hi @YaBoyRock, Glad to hear you were able to find the demo's in question. best regards, Jon
  24. Hi @YaBoyRock, There are two demo's available for the DJTG one is called DJTGDemo and the other is called DJTGTwoWireDemo as shown in the attached screen shot below. Its my understanding that the DJTGDemo is made to work with a 4-wire set up. best regards, Jon
  25. Hi @YaBoyRock, Welcome to the Digilent Forums! It my understanding that the DtjgDemo.cpp is made for 4-wire. Is there a specific function in the DjtgTwoWireDemo.cpp that you are interested in? Have you looked at the Digilent Adept JTAG Interface(DJTG) Programmer's Reference found in the \digilent.adept.sdk_v2.4.2\doc folder? best regards, Jon