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Everything posted by jpeyron

  1. jpeyron

    Data compression

    Hi @Mukul, I have worked a little bit with data compression in software. I am not very experienced with using data compression in FPGA's. Hopefully one of the more experienced community members or staff will have some good input for you. best regards, Jon
  2. jpeyron

    PCIE on CMOD-A735T

    Hi @Charles Li, Welcome to the Digilent Forums! To meet a specific tier of development board not all of the FPGA's capabilities are facilitated in every Digilent FPGA development board. Here is the Cmod A7 resource center. On the schematic for the Cmod A7 you can see on page 3 what pins have been routed on banks 14, 16, 34 and 35. Here is a list of Digilent boards that have the transceivers routed. Zedboard Nexys Video Genesys 2 NetFPGA Sume best regards, Jon
  3. jpeyron

    SDK issue

    Hi @Kris Persyn, It looks like your first first screen shot with the application sw you selected empty template. You will need to add or import a main.c under the scr folder. If you expand your bsp as well as the HW platform you should be able to find the libraries included in the IP cores in your HW platform. best regards, Jon
  4. Hi @Kobi18210, Sorry for the delayed response. We do not have a project that directly transfers data through the ethernet. We have used the echo server project which should be similar process as with this tutorial here. I have attached an altered echo.c file as a potential reference. Another option would be to use an embedded linux platform like petalinux here. best regards, Jon echo.txt
  5. Hi @Sami Malik, Can you attach a screen shot of your bram IP Core setting and memory addresses for the bram. best regards, Jon
  6. jpeyron


    Hi @eray, @hamster's MPU6050/Basys 3 is a good start to an interesting project. I would suggest converting audio files to a coe file using something like matlab or a prython script. Then in vivado is a bram with the coe file. Here is a xilinx forum thread that discusses this. best regards, Jon
  7. Hi @birca123, I reached out to one of my co-workers which happens to be currently having a similar issue with the Video Timing Controller on their project. We will be looking into this further but currently havent found a cause. We also would suggest to reach out to Xilinx about the Video Timing Controller hanging as well. best regards, Jon
  8. Hi @hearos, Are you using the SD card reader that is on the Nexys 4 DDR or a Pmod SD or Pmod MicroSD on pmod port JA? If you are trying to us the SD card reader on the Nexys 4 DDR then you will want to use the onboard Micro SD Slot under external memory on the board tab. I have attached a screen shot of this. If you are using a Pmod Sd or Pmod MicroSD on port JA you should not need a XDC to constrain these pins since the boards files along with the vivado library IP's configure this for you. best regards, Jon
  9. Hi @Cuikun LIN, Here is a forum thread that discusses Labview and AD2 sample code. Here is a forum thread that discusses the WaveForms Runtime/SDK which can be accessed from LabView directly without Python which is on here. The provided examples in the SDK are mostly in Python which you might be helpful. best regards, Jon
  10. Hi @mikeWylie, Unfortunately we have not used the AD9114-DPG2-EBZ with the AD-DAC-FMC-ADP-ND adapter card. FMC's on our boards like the Nexys Video are designed to meet the 57.1 spec. The Nexys Video has a low pin count(LPC) FMC. I would also suggest contacting Analog Devices to get their input as well. best regards, Jon
  11. Hi @mufasir_qureshi, Welcome to the Digilent Forums! Could you attach all of the HDL. Can you be more descriptive about your project. best regards, Jon PS- one of my first verilog SPI controller i missed assigning the signal as an inout. Instead I had assigned it as an input.
  12. Hi @NeedlessBird, Glad to to hear that changing the Vivado version resolved the SDK driver issue. Thank you for sharing what you had to do to resolve this issue. best regards, Jon
  13. Hi @patelviv, I have moved your thread to a section where more experienced embedded linux engineers look. Here is a non digilent tutorial that might be helpful. best regards, Jon
  14. Hi @michaelgood411, Welcome to the Digilent Forums! I have moved your thread to a section where more experienced embedded linux engineers look. best regards, Jon
  15. jpeyron

    CPR 290-006

    Hi @Sergei, Welcome to the Digilent forums! I believe that the 1:19 Gear Ratio DC Motor/Gearbox has 1 pulse per revolution. Here and here are forum thread that discusses the CPR. best regards, Jon
  16. Hi @Arjun, I typically use standalone applications. I would not have a lot of information on this topic. Here and here are xilinx forum threads where they discuss a similar issues. best regards, Jon
  17. Hi @SGY, Welcome to the Digilent Forums! The Zedboard is a collaboration between a few companies. Due to this situation, there are a two places to look for good documentation. Here is the Digilent resource center for the Zedboard. The Avnet site is . The ZYNQ book was written for the Zedboard and the Zybo Zynq boards. The Zedboard OLED demo is written in Verilog. I would also look at the FPGA4FUN and Asic world for more basic non specific board HDL code. The Zedboard has a ZYNQ processor where some of the components like the DDR and USB UART bridge are tied directly to the Arm Core. These components will not be able to be used in the PL with HDL but can be used in the PS using the ZYNQ processor. I have attached an image that should help with visualizing this. best regards, Jon
  18. Hi @eric_holtzclaw, Welcome to the Digilent Forums! In your Vivado_init.tcl I would first try deleting the < in front of the F: and have the full path to the board files. Next, I would erase the "# test" text and have an empty first line of the file. It may help to make put the board files on the same drive that Vivado is on. I have attached my working .tcl file. Some of the older versions of Vivado i have installed requires a different file name(init.tcl). best regards, Jon init.tcl
  19. Hi @Allan Flippin, The USB UART connector/programming circuit on the Arty works with microblaze allowing you to debug in SDK. If you were wanting to use the JTAG HS2 as an alternative for configuring/debugging and running an application for the Arty in SDK you can do that to. I just made a simple GPIO/uart project using the JTAG HS2/JTAG connector to program the fpga and run the application which worked with one exemption. Using the JTAG HS2 did not facilitate a com port for serial communication. best regards, Jon
  20. jpeyron

    Vivado free for Artix-7?

    Hi @TerryS, Glad to hear you were able to get Vivado downloaded , installed and get through the "blinky" tutorial! Thank you for sharing what you had to do to get this done. best regards, Jon
  21. Hi @Kris Persyn, I'm glad to hear you were able to get the HDMI project up and running. Thank you for sharing what you had to do! best regards, Jon
  22. Hi @M.Mahdi.T, Welcome to the Digilent Forums! We typically do not test the max throughput metric when validating our products. Looking at the AD5933 datasheet here the Pmod IA would be limited to 1 MSPS due to the on board ADC. The main bottleneck for throughput to a host board will be the I2C communication which runs at 400 KHz. Here is a good forum thread for using the Pmod IA with the Raspberry PI with code and hints for use , setup and calibration. Here is the resource center for the Pmod IA which has the Raspberry PI code as well. best regards, Jon
  23. Hi @PG_R, I have connected many different fpga's to my PC through Ethernet using a standard Ethernet cable. I believe a regular ethernet cable will do just fine. The difficult process will be facilitating the ethernet communication. That is why I suggested using the petalinux project linked above. best regards, Jon
  24. Hi @Allan Flippin, Here is the VHDL code for the UART TX from our GPIO demo for the Arty-A7-100T which sets the tx baud rate to 9600. I have not used auto baud detection since typically we dictate the baud rate in our projects. best regards, Jon
  25. Hi @Allan Flippin, If you use the Arty-A7 35T or 100T or the Arty-S7 50T or 25T you can use a HDL(Verilog/VHDL) UART controller to communicate through the USB UART bridge. ZYNQ FPGA's have some of the components on the board tied directly to the Arm processor(PS). The DDR3 and USB UART bridge would be included in these components. With ZYNQ FPGA's you can not use the PL to directly use the USB UART bridge. I have attach an image that is a good reference on the ZYNQ processor. To use the USB UART bridge with the Arty-Z7 20 or Arty-Z7 10 you would need to use the Zynq processor. Here is the getting started with ZYNQ tutorial for the Zybo that can easily be used with the Arty-Z7 . The GSWZ tutorial shows how to use the PS to communicate through the USB UART bridge. Here is the Arty-Z7 , Arty-A7 and Arty-S7 resource centers. best regards, Jon