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Everything posted by jpeyron

  1. jpeyron

    Pmod wifi

    Hi @harika, What WIFI IP Core example are you currently using? If the example is the HTTPserver please attach screen shots of your HTTPServerConfig.h as well as deWebIOServerSrc.cpp. Please attach screen shots of your Vivado block design along with your SDK. best regards, Jon
  2. Hi @tmwhitt, To verify the Pmod AD1 is correctly working please use the Pmod DA1 IP Core with the Pmod Port JA using tutorial link above. Using the Pmod Ad1 IP Core are you getting expected results? Also please attach a picture of you physical set up and Verilog code as well if possible. best regards, Jon
  3. Hi @shahad, I split this thread here so we are not posting on a completed thread. Please attach screen shots of your block design and the top, xdc file. Here is a VHDL Nexys 4 DDR project that uses the USB UART bridge. best regards, Jon
  4. Hi @libswig, Instead of adding the Cora Z7 XDC you should add the XDC file for the ZCU104 found here. I attached a screen shot showing that you will need to expand the associated files to be able to select the xdc for the ZCU104. You should use the Cora Z7 XDC as a reference of what pins will need to be uncommented and how to set up the ZCU104 xdc. I believe you will need to add the clocking wizard from the IP catalog under the flow navigator. Use the settings from the attached screen shots above. best regards, Jon
  5. Hi @Tim S., I reached out to a co-worker that got the same error as you. We dug further into my licenses and it turns out that I have the MIPI licenses and that is why i was not having issues. We also reached out to our content team which suggested to utilize the petalinux releases which include already generated bitstreams and hardware information so you would not need the licenses. As it stands now it sounds like if you are wanting to instead alter the linux base design or use the linux base design for a different linux platform then you would either need to strip out the licensed content or purchase the licenses. In the next few days I will be working on verifying that the petalinux release will not have the licensing issues that are in having in the zybo z7 20 base linux design. best regards, Jon
  6. Hi @mnt, Welcome to the Digilent forums! Are you trying to add a VHDL entity to a zynq processor block design? If that is a yes then right click on an empty portion of the block design and select add a module. Then select the VHDL file. Here is a good YouTube video about this process. best regards, Jon
  7. jpeyron


    Hi @revathi, Here is an article by real digital that provides some additional information about the XADC and averaging. best regards, Jon
  8. Hi @tmwhitt, Welcome to the Digilent forums! To add to @JColvin's post I would suggest looking at a community members ( @hamster ) project here. It is a completed VHDL project that should help with your Verilog project. Are you trying to use both channels? We also have an Pmod AD1 IP Core here found in the Vivado library here . The Getting Started with Digilent Pmod IPs tutorial should be helpful with using the Pmod AD1 IP Core. best regards, Jon
  9. Hi @neroangelo296, Welcome to the Digilent Forums! I moved this thread to a section for FPGA questions. Here is the FMC PCAM Adapter which will allow you to use the PCAM-5C with the Zedboard. Here is the FMC-HDMI that also might fit your needs as well. best regards, Jon
  10. Hi @PoojaN, Welcome to the digilent Forums! 1) Are you programming the QSPI flash through SDK or through Vivado? 2) Here is the Arty Programming Guide and the How To Store Your SDK Project in SPI Flash that should help depending on what type of project you are using. best regards, Jon
  11. Hi @sreehari, Welcome to the Digilent Forums! As of yet I haven't used the LWiP with MDIO commands. Here is a forum thread that discusses MDIO with the Arty ethernet using linux and Here is a non-digilent forum thread that might be helpful. best regards, Jon
  12. Hi @Ram, I have not altered the size of the send buffer for the LWiP. I would suggest reaching out to xilinx about altering the send buffer with their IP. Here is a a xilinx wiki ( wiki ) and here is a forum thread that might be helpful as well. best regards, Jon
  13. Hi @djc678, Welcome to the digilent forum! I have moved this thread to a sub-section where more experienced embedded linux engineers look. best regards, Jon
  14. Hi @osmaan_khan, Here is a forum thread that discusses using the ZYNQ ps with the XADC. There are links to other threads with working zynq xadc projects along with a non-digilent tutorial and the ZYNQ book. best regards, Jon
  15. Hi @Nabil, Welcome to the digilent forums! We have reached out to more experience embedded linux engineers to see if they have some input for this thread. best regards, Jon
  16. jpeyron

    zybo image processing

    Hi @lokender, I believe this is stating that the bus width is different from the axi4 vid out and the stream_out-TDATA field. Here is a xilinx forum thread where they had a similar issue. Here is the Zybo resource center. Here is our SDSoC projects which has a sobel filter project for the Zybo but it is done in Vivado 2015.4. best regards, Jon
  17. Hi @Tim S., The IP Cores provided by Digilent should not have a cost. Here is a forum thread that describes these MIPI altered IP Cores. Are you able to generated a bitstream with the Zybo Z7-20 PCAM-5C project here(use the Vivado 2017.4 version)? I believe this project uses the same altered MIPI IP Cores. best regards, Jon
  18. HI @Grensv, Our design engineer looked at the attached logs and the endpCmd failed error message suggests a USB data transfer error. They suspect that this is related to using Virtual Box. Their only suggestion is to try running the dadutil or djtgcfg commands with sudo and see if it’s a permissions problem. best regards, Jon
  19. Hi @Ram, I believe it is the size of the tpcb which is used in the echo.c with the tcp_sndbuf and tcp_recv. I have attached an altered echo.c file that looks for two different strings and send a specific response when it gets the two different strings. best regards, Jon echo.txt
  20. Hi @jopho, I have not worked with a ZYNQ Ultrascale development board as of yet. Here is a forum thread on how to add a different FPGA family to an IP core. This thread should be helpful for adding the Ultrascale family to the DVI2RGB, RGB2DVI IP Cores. I am not aware of any architecture differences between the ZYNQ and the ZYNQ Ultrascale boards in regards to the DVI2RGB, RGB2DVI IP Cores here. best regards, Jon
  21. Hi @shahad, In Digilent Artix-7 fpga development boards like the Nexys 4 DDR you are able to use the USB UART bridge with VHDL/Verilog. Here is the resource center for the Nexys 4 DDR. Here is a Verilog project that uses the USB UART bridge with the Nexys 4 DDR. best regards, Jon
  22. Hi @Oblio, Welcome to the Digilent forums! Best regards, Jon
  23. Hi @Tim S., What version of Vivado are you using? The Zybo-Z7-20-base-linux project was created for and using Vivado 2017.4. best regards, Jon
  24. Hi @JamieJ, Welcome to the Digilent Forums! I moved your thread to a section where more AD2 experienced engineers look. best regards, Jon
  25. Hi @AndreaER, Welcome to the digilent forums! I have moved your thread to a section where more experience waveform engineers look. best regards, Jon